參數(shù)資料
型號: μPD26401
廠商: NEC Corp.
英文描述: 1M-Bit SRAM and 2M-Bit MASK ROM COMBO Chip(1M位SRAM 和2M位MASK ROM)
中文描述: 100萬位的SRAM和2M位掩膜ROM集成芯片(100萬位的SRAM和200萬位掩膜ROM)
文件頁數(shù): 10/20頁
文件大?。?/td> 119K
代理商: ΜPD26401
10
μ
PD26401
RAM Selected (/ROMCS = H, /RAMCS = L)
RAM Read Cycle (1) (V
CC
= 1.8 to 2.2 V, T
A
=
10 to
+
70 °C)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Read cycle time
t
RC
500
ns
Address access time
t
ACC
500
ns
Chip enable access time
t
RAMCS
500
ns
Output enable access time
t
OE
150
ns
Output hold time
t
OH
0
ns
Output disable time
t
DF
0
100
ns
/RAMCS to output low impedance
t
LZ
10
ns
/OE to output low impedance
t
OLZ
5
ns
Remark
t
DF
is the time from inactivation of /RAMCS or /OE to high-impedance state output.
RAM Read Cycle (2) (V
CC
= 2.2 to 2.7 V, T
A
=
10 to
+
70 °C)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Read cycle time
t
RC
375
ns
Address access time
t
ACC
375
ns
Chip enable access time
t
RAMCS
375
ns
Output enable access time
t
OE
125
ns
Output hold time
t
OH
0
ns
Output disable time
t
DF
0
100
ns
/RAMCS to output low impedance
t
LZ
10
ns
/OE to output low impedance
t
OLZ
5
ns
Remark
t
DF
is the time from inactivation of /RAMCS or /OE to high-impedance state output.
RAM Read Cycle (3) (V
CC
= 2.7 to 3.3 V, T
A
=
10 to
+
70 °C)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Read cycle time
t
RC
250
ns
Address access time
t
ACC
250
ns
Chip enable access time
t
RAMCS
250
ns
Output enable access time
t
OE
100
ns
Output hold time
t
OH
0
ns
Output disable time
t
DF
0
100
ns
/RAMCS to output low impedance
t
LZ
10
ns
/OE to output low impedance
t
OLZ
5
ns
Remark
t
DF
is the time from inactivation of /RAMCS or /OE to high-impedance state output.
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