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參數(shù)資料
| 型號(hào)： | μPD26401 |
| 廠商： | NEC Corp. |
| 英文描述： | 1M-Bit SRAM and 2M-Bit MASK ROM COMBO Chip(1M位SRAM 和2M位MASK ROM) |
| 中文描述： | 100萬位的SRAM和2M位掩膜ROM集成芯片（100萬位的SRAM和200萬位掩膜ROM） |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 119K |
| 代理商： | ΜPD26401 |
12
μ
PD26401
RAM Write Cycle (1) (V
CC
= 1.8 to 2.2 V, T
A
=
10 to
+
70 °C)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Write cycle time
t
WC
500
ns
Chip enable to end write
t
RAMCW
300
ns
Address valid to end of write
t
AW
300
ns
Address setup time
t
AS
0
ns
Write pulse width
t
WP
300
ns
Write recovery time
t
WR
0
ns
Data valid to end of write
t
DW
125
ns
Data hold time
t
DH
0
ns
/WE to output in high impedance
t
WHZ
125
ns
Output active from end of write
t
OW
5
ns
RAM Write Cycle (2) (V
CC
= 2.2 to 2.7 V, T
A
=
10 to
+
70 °C)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Write cycle time
t
WC
375
ns
Chip enable to end write
t
RAMCW
250
ns
Address valid to end of write
t
AW
250
ns
Address setup time
t
AS
0
ns
Write pulse width
t
WP
250
ns
Write recovery time
t
WR
0
ns
Data valid to end of write
t
DW
110
ns
Data hold time
t
DH
0
ns
/WE to output in high impedance
t
WHZ
100
ns
Output active from end of write
t
OW
5
ns
RAM Write Cycle (3) (V
CC
= 2.7 to 3.3 V, T
A
=
10 to
+
70 °C)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Write cycle time
t
WC
250
ns
Chip enable to end write
t
RAMCW
200
ns
Address valid to end of write
t
AW
200
ns
Address setup time
t
AS
0
ns
Write pulse width
t
WP
200
ns
Write recovery time
t
WR
0
ns
Data valid to end of write
t
DW
100
ns
Data hold time
t
DH
0
ns
/WE to output in high impedance
t
WHZ
75
ns
Output active from end of write
t
OW
5
ns
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