- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382773 > ZPSD611(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) PDF資料下載
參數(shù)資料
| 型號： | ZPSD611(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細胞（可編程邏輯，零功耗，4K的位的SRAM，26余個可編程輸入/輸出，通用PLD的有63個輸入） |
| 文件頁數(shù)： | 7/98頁 |
| 文件大?。?/td> | 484K |
| 代理商： | ZPSD611(V)E1 |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
ZPSD6XX(V) Family
12-7
The following table describes the pin names and pin functions of the ZPSD6XX(V). Pins
that have multiple names and/or functions are defined by configuration.
Table 2.
ZPSD6XX(V) Pin
Descriptions
Pin Name
Pin
Type
Function Description
ADIO0–7
30–37
I/O
Address/Data Port, interface to Microcontroller Bus
1. Input pins for multiplexed low order address/data byte.
ALE or AS latches address A0-7. The PSD drives data
out only if read is active and one of the internal PSD
functional blocks is selected.
2. Address A0-7 inputs for non-multiplexed bus or 80C251
mode
3. A4/D0-A11/D7 inputs in 80C51XA mode
4. Address (or latched address) inputs to ZPLD
ADIO8–15
39–46
I/O
Address/Data Port, interface to Microcontroller Bus
1. Address A8-15 inputs in 8-bit data bus mode, or as
multiplexed high order address/data byte inputs in 16-bit
data bus mode. ALE or AS latches address A8-15.
The PSD drives data out only if read is active and one of
the internal PSD functional blocks is selected.
2. Address A8-15 inputs in non-multiplexed bus mode
3. AD8-AD15 inputs in 80C251 mode
4. A12-A19 or A12/D8 - A19/D15 inputs in 80C51XA mode
5. Address ( or latched address) inputs to ZPLD
CNTL0)
47
I
Write Input pin with multiple configurations. Depending on
the MCU interface selected, this pin can be:
1. WR – active low write input
2. R_W – read/write pin, low for write bus cycle
3. WRL – for 16 bit data bus only, write to low byte, active low
4. Control signal (CNTL0) input to ZPLD
(WR,
R_W,
WRL)
CNTL1
50
I
Read or Data Strobe Input pin with multiple configurations.
Depending on the MCU interface selected, this pin can be:
1. RD – active low read input
2. E – E clock input.
During a write bus cycle, E is high and R/W is low
During a read bus cycle, E is high and R/W is high
3. DS – Data Strobe, active low
4. LDS – Strobe for low data byte, 16-bit data bus mode,
active low
5. PSEN – Program Select Enable, active low in read bus
cycle (80C251 configuration)
6. Control signal (CNTL1) input to ZPLD
(RD,
E,
DS,
LDS,
PSEN)
CNTL2
49
I
Read or other Control input pin with multiple configurations.
Depending on the MCU interface selected, this pin can be:
1. PSEN – Program Select enable, active low in code fetch
bus cycle
2. BHE – High byte enable, 16-bit data bus
3. UDS – Strobe for high data byte, 16-bit data bus mode,
active low
4. SIZ0 – Byte enable input
5. Control signal (CNTL2) input or general input to ZPLD
(PSEN,
BHE,
UDS,
SIZ0)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZPSD612(V)E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| ZPSD613(V)E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| ZPSD813F1V | Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM) |
| ZR33771GC-40 | Cell Rectifier Diodes |
| ZR33771GM-20 | Cell Rectifier Diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD612E1-15L | 制造商:WSI 功能描述: |
| ZPSD612E1V-20L | 制造商:WSI 功能描述: |
| ZPSD613E1-15J | 制造商:WSI 功能描述: |
| ZPSD613E1-15L | 制造商:WSI 功能描述: |
| ZPSD613E1-70J | 制造商:WSI 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。