參數(shù)資料
型號(hào)： ZPSD611(V)E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入）
文件頁(yè)數(shù)： 30/98頁(yè)
文件大?。?/td> 484K
代理商： ZPSD611(V)E1
ZPSD6XX(V) Family
12-30
Microcontroller Interface Examples
Figures 13 through 20 show examples of the basic connections between the ZPSD6XX(V)
and some popular microcontrollers. The ZPSD6XX(V) control input pins are labeled as the
microcontroller function for which they are configured. The MCU interface is specified using
the PSDsoft tools. The PC2 pin should be grounded if Vstby is not used.
80C31
Figure 13 shows the interface to the 80C31 which has an 8-bit multiplexed address/data
bus. The lower address byte is multiplexed with the data bus. The microcontroller RD and
WR signals may be used for accessing internal SRAM and I/O Ports while the PSEN signal
is used to read the EPROM. The ALE input (Port D PD0) latches the address. Refer to the
Memory Section for additional 80C31 operating modes.
68HC11
Figure 14 shows an interface to an 68HC11 where the ZPSD6XX(V) is configured in 8-bit
multiplexed mode with E and R/W settings. The ECSPLD can generate the READ and
WR signals for external on board devices. The CNTL2 pin is not used and can be used
as a ZPLD input.
80C196
In Figure 15, the Intel 80C196 microcontroller, which has a multiplexed sixteen-bit bus,
is shown connected to a ZPSD6XX(V). The BHE signal is used for high data byte selection.
Port pins can be configured in the PSDabel as ZPLD outputs to control the READY and
BUSWIDTH pins of the 80C196.
MC68331
Figure 16 shows a Motorola MC68331 with non-multiplexed sixteen-bit data bus and
24-bit address bus. The data bus from the MC68331 is connected to Port A (D0–7) and
Port B (D8–15). The SIZ0 and A0 inputs determine the high/low byte selection.
80C51XA
The Philips 80C51XA microcontroller family has an 8 or 16 bit multiplexed bus that
supports burst cycles. Address bits A[3:0] are not multiplexed while A[19:4] are multiplexed
with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed with data bits
D[7:0].
The 80C51XA can be configured to operate with a ZPSD6XX(V) in an 8-bit (shown in
Figure 17) or 16-bit (shown in Figure 18) data mode. With a 16-bit data bus, the 80C51XA’s
WRH pin is connected to the PC7 pin on the ZPSD6XX(V). Pin PA0 is grounded and not
used.
The 80C51XA improves bus throughput and performance by executing Burst cycles to
fetch codes from memory. In Burst cycles, address A19–4 are latched internally by the
ZPSD6XX(V), while the 80C51XA changes the A3–0 lines to sequentially fetch up to
16 bytes of code. The PSD access time is then measured from address A3–A0 valid
to data in valid. The ZPSD6XX(V) bus timing requirement in Burst cycle is identical to the
normal bus cycle except the address set up or hold time with respect to ALE is not required.
Bus Interface
(cont.)
相關(guān)PDF資料
PDF描述
ZPSD612(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
ZPSD613(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
ZPSD813F1V Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM)
ZR33771GC-40 Cell Rectifier Diodes
ZR33771GM-20 Cell Rectifier Diodes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD612E1-15L 制造商:WSI 功能描述:
ZPSD612E1V-20L 制造商:WSI 功能描述:
ZPSD613E1-15J 制造商:WSI 功能描述:
ZPSD613E1-15L 制造商:WSI 功能描述:
ZPSD613E1-70J 制造商:WSI 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*