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| 型號(hào)： | ZPSD611(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入） |
| 文件頁(yè)數(shù)： | 14/98頁(yè) |
| 文件大?。?/td> | 484K |
| 代理商： | ZPSD611(V)E1 |
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ZPSD6XX(V) Family
12-14
The ZPSD6XX(V)
Functional
Blocks
The ZPSD6XX(V) consists of five major functional blocks:
J
ZPLD Block
J
Bus Interface
J
I/O Ports
J
Memory Block
J
Power Management Unit
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
ZPLDs
The Zero Power PLDs (ZPLDs) bring programmable logic functionality to the ZPSD6XX(V).
After specifying the logic for the ZPLDs by using the PSDabel tool in PSDsoft, the logic
configuration is programmed into the device and available when power is applied.
The ZPLDs (DPLD, ECSPLD and GPLD) consist of an AND array. The GPLD architecture
includes 12 Output Micro
Cells in addition to the AND array. There are 23 Input
Micro
Cells that can be configured as inputs to the ZPLD. Figure 4 shows the organization
of the ZPLD.
The AND array is used to form product terms specified using the PSDabel tool in the
PSDsoft development system. When the inputs used in a term are true, the output is active.
The GPLD Input Bus consists of 63 signals as shown in Table 6. Both the true and
complement value of inputs are available to the AND array. The DPLD and ECSPLD Input
Busses consist of fewer inputs and are a subset of the 63 inputs.
Input Source
Input Name
Number of Signals
MCU Address Bus
A[15:0]*
16
MCU Control Signals
CNTL[2:0]
3
Reset
RST
1
Power Down
PDN
1
I/O Ports Inputs (Input Micro
Cells)
PA[7:0], PB[7:0]
PC[7:3], PC[1:0]
23
Port D Inputs
PD[2:0]
3
Page Register
PGR[3:0]
4
Port A or B Micro
Cell Feedback
Port C Micro
Cell Feedback
MCELLAB.FB[7:4]
4
MCELLC.FB[7:0]
8
Table 6. GPLD Inputs
*
NOTE:
The address inputs are A[19:4] in 80C51XA mode.
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