參數(shù)資料
型號: ZPSD211R
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,可加密,零功耗,12個可單獨配置I/O)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備(可編程邏輯,可加密,零功耗,12個可單獨配置的I / O)
文件頁數(shù): 12/32頁
文件大?。?/td> 149K
代理商: ZPSD211R
PSD211R
12
The PSD211R has three I/O ports (Ports A, B, and C) that are configurable at the bit level.
This permits great flexibility and a high degree of customization for specific applications. The
following is a description of each port. Figure 4 shows the pin structure of Port A.
Port A
The default configuration of Port A is I/O. In this mode, every pin can be set as an input or
output by writing into the respective pin’s direction flip flop (DIR FF, in Figure 4). As an
output, the pin level can be controlled by writing into the respective pin’s data flip flop
(DFF, in Figure 4). When DIR FF = 1, the pin is configured as an output. When DIR FF = 0,
the pin is configured as an input. The controller can read the DIR FF bits by accessing the
READ DIR register; it can read the DFF bits by accessing the READ DATA register. Port A
pin levels can be read by accessing the READ PIN register. For addressing information, refer
to Table 6.
Alternatively, each bit of Port A can be configured as a low-order latched address bus bit.
The address is provided by the port address latch, which latches the address on the trailing
edge of ALE. PA0–PA7 can become A0–A7, respectively. This feature enables the user
generate low-order address bits to access external peripherals or memory that require
several low-order address lines.
Port Functions
Figure 4. Port A Pin Structure
READ PIN
PORT A PIN
ENABLE
ADDR
OUT
READ DATA
WRITE DATA
ALE
READ DIR
WRITE DIR
RESET
CK
D
R
G
D
R
D
CK
R
I
N
T
E
R
N
A
L
A
D
D
R
/
D
A
T
A
B
U
S
A
D
0
/
A
D
7
DFF
LATCH
DIR
FF
CONTROL
MUX
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