參數(shù)資料
型號: Z9973BA
英文描述: DIODE TVS 15V 500W UNI-DIR
中文描述: 第十二章分布式輸出時鐘驅(qū)動器| TQFP封裝| 52PIN |塑料
文件頁數(shù): 8/11頁
文件大?。?/td> 63K
代理商: Z9973BA
3.3V, 125MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07089 Rev. **
9/15/2000
Page 8 of 11
Z9973
Power Management
The individual output enable / freeze control of the Z9973 allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The
serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT
outputs can not be frozen with the serial port, this avoids any potential lock up situation should an error occur in the
loading of the serial data. An output is frozen when a logic ‘0’ is programmed and enabled when a logic ‘1’ is written. The
enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks.
The serial input register is programmed through the SDATA input by writing a logic ‘0’ start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on
the rising edge of SCLK.
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Start
Bit
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