參數(shù)資料
型號(hào)： Z9973BA
英文描述： DIODE TVS 15V 500W UNI-DIR
中文描述： 第十二章分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 52PIN |塑料
文件頁數(shù)： 4/11頁
文件大?。?/td> 63K
代理商： Z9973BA
3.3V, 125MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07089 Rev. **
9/15/2000
Page 4 of 11
Z9973
AC Parameters
1
SYMBOL
Tr / Tf
Fref
FrefDC
Fvco
Tlock
Tr / Tf
Fout
PARAMETER
TCLK Input Rise / Fall
Reference Input Frequency
Reference Input Duty Cycle
PLL VCO Lock Range
Maximum PLL lock Time
Output Clocks Rise / Fall Time
3
Maximum Output Frequency
MIN
TYP
MAX
3.0
Note 2
75
480
10
1.2
125
120
80
60
TCYCLE/2
+ 750
10
UNITS
ns
MHz
%
MHz
ms
ns
MHz
CONDITIONS
Note 2
25
200
0.15
-
0.8V to 2.0V
Q (
÷
2)
Q (
÷
4)
Q (
÷
6)
Q (
÷
8)
FoutDC
Output Duty Cycle
3
TCYCLE/2
– 750
2
ps
tpZL,
tpZH
tpLZ,
tpHZ
TCCJ
Output Enable Time
3
(all outputs)
Output Disable Time
3
(all outputs)
Cycle to Cycle Jitter
3
(peak to peak)
Any Output to Any Output Skew
3,4
Propagation Delay
4,5
ns
2
8
ns
+/- 100
ps
TSKEW
Tpd
350
175
330
270
ps
ps
PECL_CLK
TCLK0
TCLK1
VDD = VDDC = 3.3V +/- 5%, TA = -40
°
C to +85
°
C
-225
-70
-130
-25
130
70
QFB =(
÷
8)
Note 1:
Parameters are guaranteed by design and characterization. Not 100% tested in production.
Note 2:
Maximum and minimum input reference is limited by VCO lock range.
Note 3:
Outputs loaded with 30pF each.
Note 4:
50
transmission line terminated into VDDC/2.
Note 5:
Tpd is specified for a 50MHz input reference. Tpd does not include jitter.
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相關(guān)代理商/技術(shù)參數(shù)
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Z9975CA 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 150MHz, Multi-Output Zero Delay Buffer
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