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參數(shù)資料
| 型號： | Z9973BA |
| 英文描述： | DIODE TVS 15V 500W UNI-DIR |
| 中文描述： | 第十二章分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 52PIN |塑料 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 63K |
| 代理商： | Z9973BA |
3.3V, 125MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07089 Rev. **
9/15/2000
Page 5 of 11
Z9973
Description
The Z9973 has an integrated PLL that provides low skew and low jitter clock outputs for high performance
microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT,
provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO
is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125MHz.
The phase detector compares the input reference clock to the external feedback input. For normal operation, the
external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples
of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs, refer to Frequency Table. The VCO
frequency is then divided down to provide the required output frequencies. These dividers are set by SELA(0,1),
SELB(0,1), SELC(0,1) select inputs, see table 2 below. For situations were the VCO needs to run at relatively low
frequencies and hence might not be stable, assert VCO_SEL low to divide the VCO frequency by 2. This will maintain
the desired output relationships, but will provide an enhanced PLL lock range.
The Z9973 is also capable of providing inverted output clocks. When INV_CLK is asserted high, QC2 and QC3 output
clocks are inverted. These clocks could be used as feedback outputs to the Z9973 or a second PLL device to generate
early or late clocks for a specific design. This inversion does not affect the output to output skew.
VCO_SEL
0
0
0
0
1
1
1
1
SELA1
0
0
1
1
0
0
1
1
SELA0
0
1
0
1
0
1
0
1
QA
SELB1
0
0
1
1
0
0
1
1
Table 2
SELB0
0
1
0
1
0
1
0
1
QB
SELC1
0
0
1
1
0
0
1
1
SELC0
0
1
0
1
0
1
0
1
QC
VCO/8
VCO/12
VCO/16
VCO/24
VCO/4
VCO/6
VCO/8
VCO/12
VCO/8
VCO/12
VCO/16
VCO/20
VCO/4
VCO/6
VCO/8
VCO/10
VCO/4
VCO/8
VCO/12
VCO/16
VCO/2
VCO/4
VCO/6
VCO/8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Z9974 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 125-MHz, Multi-Output Zero Delay Buffer |
| Z9974CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FOURTEEN DISTRIBUTED-OUTPUT CLOCK DRIVER|TQFP|52PIN|PLASTIC |
| Z9975 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 150MHz, Multi-Output Zero Delay Buffer |
| Z9975CA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 150MHz, Multi-Output Zero Delay Buffer |
| Z99SC61235 | 制造商:MINI CIRCU 功能描述:NEW |
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