參數(shù)資料
型號: Z9973BA
英文描述: DIODE TVS 15V 500W UNI-DIR
中文描述: 第十二章分布式輸出時鐘驅(qū)動器| TQFP封裝| 52PIN |塑料
文件頁數(shù): 1/11頁
文件大?。?/td> 63K
代理商: Z9973BA
3.3V, 125MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07089 Rev. **
9/15/2000
Page 1 of 11
Z9973
Product Features
Output Frequency up to 125MHz
Supports PowerPC
TM
, and Pentium
TM
Processors
12 Clock Outputs: Frequency Configurable
Configurable Output Disable
Two Reference Clock Inputs for Dynamic Toggling
Oscillator or PECL Reference Input
Spread Spectrum Compatible
Glitch-free Output Clocks Transitioning
3.3V Power Supply
Pin Compatible with MPC973
Industrial Temp. Range: -40°C to +85°C
52-Pin TQFP Package
Block Diagram
Frequency Table *
VCO_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FB_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table 1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F
VCO
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
* x = the reference input frequency, 200MHz < F
VCO
<
480MHz.
Pin Configuration
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VDD
F
S
V
Q
V
Q
S
S
Q
V
Q
V
I
S
S
S
S
Q
V
Q
V
Q
V
Q
V
V
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
Z9973
REF_SEL
0
1
0
1
Phase
Detector
VCO
LPF
Sync
Frz
D Q
QA0
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
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