參數(shù)資料
型號: Z9025900ZEM
英文描述: SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:600V; On-State RMS Current, IT(rms):35A; Peak Non Repetitive Surge Current, Itsm:500A; Gate Trigger Current Max, Igt:40uA
中文描述: 消費(fèi)性IC
文件頁數(shù): 5/30頁
文件大?。?/td> 938K
代理商: Z9025900ZEM
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
PS001300-TVC1099
Preliminary
5
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Code Development Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Z90255-Based TV System Application . . . . . . . . . . . . . . . . . . . . . . . . . 10
Z90255 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Z90255 and Z90251 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register File Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Positive and Negative Sync Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Second Color Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Mesh On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Video Fade (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Character Pixel map in CGROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Example of a Multiple Character Icon . . . . . . . . . . . . . . . . . . . . . . . . . 39
Smoothing Effect on 2X Character Size . . . . . . . . . . . . . . . . . . . . . . . . 40
VRAM Data Path for 512 Character Set . . . . . . . . . . . . . . . . . . . . . . . . 43
H
SYNC
and V
SYNC
Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Bidirectional Port Pin Pad Multiplexed with I2C Port . . . . . . . . . . . . . 54
Pulse Width Modulator Timing Diagram, 6 Bit . . . . . . . . . . . . . . . . . . 73
Pulse Width Modulator Timing Diagram, 14-Bit . . . . . . . . . . . . . . . . . 74
Analog Signals Generated from PWM Signals . . . . . . . . . . . . . . . . . . 81
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timing Requirements of External Inputs . . . . . . . . . . . . . . . . . . . . . . . 88
42-Lead Shrink Dual-in-line Package (SDIP) . . . . . . . . . . . . . . . . . . . . 89
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