參數(shù)資料
型號(hào): Z9025900ZEM
英文描述: SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:600V; On-State RMS Current, IT(rms):35A; Peak Non Repetitive Surge Current, Itsm:500A; Gate Trigger Current Max, Igt:40uA
中文描述: 消費(fèi)性IC
文件頁數(shù): 24/30頁
文件大?。?/td> 938K
代理商: Z9025900ZEM
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
PS001300-TVC1099
Preliminary
24
Bit
4
, Sync Polarity, provides the polarity of the
H
SYNC
and
V
SYNC
signals.
H
SYNC
and
V
SYNC
must have the same polarity (see Figure 7). This feature is designed to provide
flexibility for TV chassis designers.
Figure 7
Positive and Negative Sync Signals
Bit
3
, Character Size, sets the size of the characters that are displayed. Character sizes 1X,
2X, double width and double height are supported. The default value is
1X
.
To change the size of the characters in a row, alter the value of the bit during the previous
horizontal interrupt. The character size of the first row is programmed during vertical
interrupt (
V
SYNC
) processing. Character size is a row attribute.
Bits
2
,
1
, and
0
, Vertical Retrace Blanking, set a time period when the
OSD
is disabled
while the electron gun returns from the bottom to the top of the screen, and all
VBLANK
and RGB output are disabled. The blanking period is determined by counting horizontal
pulses according to the following formula:
Blanking Period=(4 x (Vertical Retrace Blanking)+2) x THL
THL:
one horizontal period
The retrace blanking bits,
OSD_CNTL (2,1,0)
must be set to deactivate the electron
guns during the retrace period.
Bit/
Field
Bit
Position R/W
Value Description
OSD Blank
7
R/W
0
1
Enable OSD - POR default
Disable OSD
VRAM Mode
6, 5
R/W
00
01
10
11
Select 10-row buffer mode
Reserved
Select 2-row buffer mode
Reserved
Sync Polarity
4
R/W
0
1
Positive
Negative
Character Size
3
R/W
0
1
1X
2X
Vertical Retrace Blanking
2, 1, 0
R/W
Retrace Blanking
Positive SYNC
Negative SYNC
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