
XRT94L33
xr
Rev.1.2.0.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
202
The “HEC Byte Calculation & Insertion” block receives either filtered User Cells or Idle cells from the
upstream circuitry, within the Transmit ATM Cell Processor block. As it receives these cells, the “HEC Byte
Calculation & Insertion” block can be configured to perform any of the following actions on these cells.
To compute and verify the HEC bytes of incoming cells from upstream circuitry within the Transmit ATM
Cell Processor block
To regenerate the HEC byte (e.g., to compute and insert the HEC bytes of incoming cells)
To add the Coset Polynomial to the HEC byte, prior to transmission via the “Transmit Data Path”
A detailed description of the HEC Byte Calculation & Insertion block is presented below.
Computing and Verifying HEC Bytes of incoming cells
As the HEC Byte Calculation & Insertion block receives ATM cells, it takes the first four bytes of each cell and
computes a CRC-8 value via the generating polynomial x
8 + x2 + x + 1.
Note:
The user has the option to have the coset polynomial x
6 + x4 + x2 + 1 modulo-2 added to the CRC-8 byte and,
insert this newly modified CRC-8 value into the fifth octet position within the cell before transmission. This
option will be discussed later in this section.
Configuring the HEC Byte Calculation & Insertion block to Check for HEC Byte Errors
If the user wishes to configure the Transmit ATM Cell Processor block to compute, verify and flag HEC byte
errors in cells originating from upstream circuitry, then they must write a “1” into Bit 6 (HEC Byte Check
Enable) within the “Transmit ATM Control – Byte 0, as depicted below.
Transmit ATM Control – Byte 0 (Address = 0xNF03)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HEC Byte
Invert
HEC Byte
Check
Enable
Parity Check
Enable
Discard Cell
upon Parity
Error
Odd Parity
Unused
Cell Payload
Scramble
Enable
R/W
R/O
R/W
0
1
0
X
0
X
If the user implements this configuration option, then the HEC Byte Calculation & Insertion Block will compute
and verify the HEC byte, within all ATM cells that it receives from the Idle Cell Generator and the Transmit
User Cell Filter blocks. If the HEC Byte Calculation & Insertion Block detects a HEC byte error, then the
Transmit ATM Cell Processor block will generate the “Detection of HEC Byte Error” Interrupt. The Transmit
ATM Cell Processor block will indicate that it is generating this interrupt by doing all of the following.
It will toggle the “INT*” output pin “LOW”.
The Transmit ATM Cell Processor block will set Bit 1 (Detection of HEC Byte Error Interrupt Status),
within the “Transmit ATM Cell Processor – Interrupt Status Register” as depicted below.
Transmit ATM Cell Processor – Interrupt Status Register (Address = 0xNF0B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Cell
Extraction
Interrupt
Status
Cell
Insertion
Interrupt
Status
Cell
Extraction
Memory
Overflow
Interrupt
Status
Cell Insertion
Memory
Overflow
Interrupt
Status
Detection of
HEC Byte
Error
Interrupt
Status
Detection of
Parity Error
Interrupt
Status
R/O
RUR