
XRT94L33
xr
Rev.1.2.0.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
386
2.3.2
RECEIVE STS-3C POH PROCESSOR BLOCK (FOR STS-3C APPLICATIONS)
The purpose of the Receive STS-3c POH Processor block is to accomplish the following.
To receive an STS-3c SPE from the Receive STS-3 TOH Processor block
To acquire and maintain the location of the STS-3c SPE, within the incoming STS-3c data-stream
To compute and verify the B3 bytes and increment performance monitor registers anytime it detects B3
byte errors.
To declare and clear the following defect conditions.
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LOP-P (Loss of Pointer)
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AIS-P (Path AIS)
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RDI-P (Path – Remote Defect Indicator)
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PLM-P (Path – Payload Label Mismatch)
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UNEQ-P (Path – Unequipped)
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TIM-P (Path – Trace Identification Mismatch)
To increment performance monitor registers anytime it detects an REI-P event.
To receive either 1-byte, 16-byte or 64-byte Path Trace Identification Messages via the J1 byte within each
incoming STS-3c SPE; and to detect and declare the TIM-P defect condition when appropriate.
Figure 90 presents an illustration of the Functional Block Diagram of the XRT94L33 Mapper IC; with the