參數(shù)資料
型號: XRT83VSH316
廠商: Exar Corporation
英文描述: 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 16-CHANNEL的T1/E1/J1短途線路接口單元
文件頁數(shù): 82/96頁
文件大小: 600K
代理商: XRT83VSH316
XRT83VSH316
PRELIMINARY
80
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.3
D5
FLS
FIFO Limit Status
The FIFO limit status is always active regardless if the interrupt
generation is disabled. This bit indicates whether the RD/WR
pointers are within 3-Bits. An interrupt will not occur unless the
FLSIE is set to "1" in the channel register 0xN04h and GIE is set to
"1" in the global register 0x0000h.
0 = No Alarm
1 = RD/WR FIFO pointers are within ±3-Bits
RO
0
D4
LCV_OF
Line Code Violation / Counter Overflow
This bit serves a dual purpose. By default, this bit monitors the line
code violation activity. However, if bit 7 in register 0x0005h is set
to a "1", this bit monitors the overflow status of the internal LCV
counter. An interrupt will not occur unless the LCV_OFIE is set to
"1" in the channel register 0xN04h and GIE is set to "1" in the glo-
bal register 0x0000h.
0 = No Alarm
1 = A line code violation, bipolar violation, or excessive zeros has
occurred
RO
0
D3
Reserved
This Bit is Reserved
RO
0
D2
AISD
Alarm Indication Signal Detection
The alarm indication signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the AIS
activity. An interrupt will not occur unless the AISIE is set to "1" in
the channel register 0xN04h and GIE is set to "1" in the global reg-
ister 0x0000h.
0 = No Alarm
1 = An all ones signal is detected
RO
0
D1
RLOS
Receiver Loss of Signal
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0xN04h and GIE is set to "1" in the global
register 0x0000h.
0 = No Alarm
1 = An RLOS condition is present
RO
0
D0
QRPD
Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0xN04h and GIE is set to "1" in
the global register 0x0000h.
0 = No Alarm
1 = A QRP is detected
RO
0
N
OTE
:
The GIE bit in the global register 0x0000h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
T
ABLE
48: M
ICROPROCESSOR
R
EGISTER
0
X
N05
H
B
IT
D
ESCRIPTION
C
HANNEL
N (0
X
N05
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
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