參數(shù)資料
型號(hào): XRT83VSH316
廠商: Exar Corporation
英文描述: 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 16-CHANNEL的T1/E1/J1短途線路接口單元
文件頁(yè)數(shù): 71/96頁(yè)
文件大小: 600K
代理商: XRT83VSH316
PRELIMINARY
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316
69
REV. P1.0.3
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits in
register 0x0009h. Therefore, if the clock selection bits are being programmed, the frequency of the PLL output
will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within
the same register while selecting the input/output clock frequency. For best results, register 0x0009h can be
broken down into two sub-registers with the MSB being bit D4 and the LSB being bits D[3:0] as shown in
Figure 43
.
N
OTE
:
Bits D[7:5] are reserved.
F
IGURE
43. R
EGISTER
0
X
0009
H
S
UB
R
EGISTERS
Programming Examples:
Example 1
: Changing bits D[7:4]
If bit D4 is the only values within the register that will change in a WRITE process, the microprocessor only
needs to initiate ONE write operation.
Example 2
: Changing bits D[3:0]
If bits D[3:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3
: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection bits D[3:0] (LSB) and then change bit D4 (MSB) on the SECOND write, or
vice-versa. No order or sequence is necessary.
T
ABLE
34: M
ICROPROCESSOR
R
EGISTER
0
X
008
H
B
IT
D
ESCRIPTION
G
LOBAL
R
EGISTER
(0
X
008
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
LCVCNT15
LCVCNT14
LCVCNT13
LCVCNT12
LCVCNT11
LCVCNT10
LCVCNT9
LCVCNT8
Line Code Violation Byte Contents[15:8]
These bits contain the MSB (bits [15:8]) of the LCV counter con-
tents for a selected channel. The channel is addressed by using
bits D[3:0] in register 0x0005h.
RO
0
0
0
0
0
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
MSB
LSB
Clock Selection Bits
Reserved, TCLKCNTL
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