參數(shù)資料
型號(hào): XRT83VSH316
廠商: Exar Corporation
英文描述: 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 16-CHANNEL的T1/E1/J1短途線路接口單元
文件頁(yè)數(shù): 55/96頁(yè)
文件大小: 600K
代理商: XRT83VSH316
PRELIMINARY
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316
53
REV. P1.0.3
6.3
The LIU may be configured into different operating modes and have its performance monitored by software
through a standard microprocessor using data, address and control signals. These interface signals are
described below in
Table 16
,
Table 17
, and
Table 18
. The microprocessor interface can be configured to
operate in Intel mode or Motorola mode. When the microprocessor interface is operating in Intel mode, some
of the control signals function in a manner required by the Intel 80xx family of microprocessors. Likewise, when
the microprocessor interface is operating in Motorola mode, then these control signals function in a manner as
required by the Motorola Power PC family of microprocessors. (For using a Motorola 68K asynchronous
processor, see
Figure 42
and
Table 22
)
Table 16
lists and describes those microprocessor interface signals
whose role is constant across the two modes.
Table 17
describes the role of some of these signals when the
microprocessor interface is operating in the Intel mode. Likewise,
Table 18
describes the role of these signals
when the microprocessor interface is operating in the Motorola Power PC mode.
The Microprocessor Interface Block Signals
T
ABLE
16: XRT83VSH316 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
COMMON
TO
BOTH
I
NTEL
AND
M
OTOROLA
M
ODES
P
IN
N
AME
T
YPE
D
ESCRIPTION
PTYPE[2:0]
I
Microprocessor Interface Mode Select Input pins
These three pins are used to specify the microprocessor interface mode. The relationship
between the state of these three input pins, and the corresponding microprocessor mode is
presented in
Table 15
.
DATA[7:0]
I/O
Bi-Directional Data Bus for register "Read" or "Write" Operations.
CSdec[2:0]
I
Chip Select Decoder Inputs
The state of these 3 pins enable the Chip Selects for additional LIU devices.
N
OTE
:
See the 84-Channel Application Section of this datasheet.
ADDR[9:0]
I
Nine-Bit Address Bus Inputs
The XRT83VSH316 LIU microprocessor interface uses a direct address bus. This address bus
is provided to permit the user to select an on-chip register for Read/Write access.
CS
I
Chip Select Input
This active low signal selects the microprocessor interface of the XRT83VSH316 LIU and
enables Read/Write operations with the on-chip register locations.
T
ABLE
17: I
NTEL
MODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
XRT83VSH316
P
IN
N
AME
I
NTEL
E
QUIVALENT
P
IN
T
YPE
D
ESCRIPTION
ALE_TS
ALE
I
Address-Latch Enable:
This active high signal is used to latch the contents on
the address bus ADDR[8:0]. The contents of the address bus are latched into the
ADDR[8:0] inputs on the falling edge of ALE.
RD_WE
RD
I
Read Signal:
This active low input functions as the read signal from the local
μ
P.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read oper-
ation has been requested and begins the process of the read cycle.
WR_R/W
WR
I
Write Signal:
This active low input functions as the write signal from the local
μ
P.
When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write
operation has been requested and begins the process of the write cycle.
RDY_TA
RDY
O
Ready Output:
This active low signal is provided by the LIU device. It indicates
that the current read or write cycle is complete, and the LIU is waiting for the next
command.
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