參數(shù)資料
型號： XRT83VSH316
廠商： Exar Corporation
英文描述： 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： 16-CHANNEL的T1/E1/J1短途線路接口單元
文件頁數(shù)： 4/96頁
文件大小： 600K
代理商： XRT83VSH316
XRT83VSH316
PRELIMINARY
I
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. P1.0.3
TABLE OF CONTENTS
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT83VSH316........................................................................................................................ 1
1.0 PIN DESCRIPTIONS ..............................................................................................................................4
2.0 CLOCK SYNTHESIZER .......................................................................................................................19
F
IGURE
2. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
C
LOCK
S
YNTHESIZER
............................................................................................ 19
3.0 RECEIVE PATH LINE INTERFACE .....................................................................................................20
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
...................................................................................................... 20
3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 20
3.1.1 INTERNAL TERMINATION......................................................................................................................................... 20
F
IGURE
4. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
.................................................................................... 21
3.2 CLOCK AND DATA RECOVERY .................................................................................................................. 22
F
IGURE
5. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK .............................................................................................. 22
F
IGURE
6. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK............................................................................................ 22
3.3 RECEIVE SENSITIVITY .................................................................................................................................. 23
F
IGURE
7. T
EST
C
ONFIGURATION
FOR
M
EASURING
R
ECEIVE
S
ENSITIVITY
........................................................................................ 23
3.4 INTERFERENCE MARGIN ............................................................................................................................. 23
F
IGURE
8. T
EST
C
ONFIGURATION
FOR
M
EASURING
I
NTERFERENCE
M
ARGIN
.................................................................................... 23
3.5 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ............................................................ 24
F
IGURE
9. I
NTERRUPT
G
ENERATION
P
ROCESS
B
LOCK
..................................................................................................................... 24
3.6 RECEIVE DIAGNOSTIC PATTERN DETECTION .......................................................................................... 25
3.6.1 RLOS (RECEIVER LOSS OF SIGNAL, LINE SIDE) .................................................................................................. 25
3.6.2 EXLOS (EXTENDED LOSS OF SIGNAL) .................................................................................................................. 25
3.6.3 AIS (ALARM INDICATION SIGNAL, LINE SIDE) ...................................................................................................... 25
3.6.4 FLSD (FIFO LIMIT STATUS DETECTION) ................................................................................................................ 25
3.6.5 LCV (LINE CODE VIOLATION DETECTION, LINE SIDE ONLY).............................................................................. 25
3.7 RECEIVE DIAGNOSTIC PATTERN GENERATION ...................................................................................... 26
3.7.1 SYSTEM SIDE AIS (SAIS).......................................................................................................................................... 26
F
IGURE
10. S
YSTEM
S
IDE
SAIS R
ECEIVE
O
UTPUT
......................................................................................................................... 26
3.7.2 ATAOS (SYSTEM AUTOMATIC TRANSMIT ALL ONES)......................................................................................... 26
F
IGURE
11. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
ATAOS F
UNCTION
............................................................................................... 26
3.7.3 SYSTEM SIDE LOS (SLOS) ....................................................................................................................................... 27
F
IGURE
12. S
YSTEM
S
IDE
SLOS R
ECEIVE
O
UTPUT
........................................................................................................................ 27
3.8 SYSTEM SIDE SPRBS RECEIVE OUTPUT ................................................................................................... 27
3.9 JITTER ATTENUATOR (IF ENABLED IN THE RECEIVE PATH) ................................................................. 28
3.10 HDB3/B8ZS DECODER ................................................................................................................................ 28
F
IGURE
13. S
INGLE
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
................................................................................... 28
F
IGURE
14. D
UAL
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
...................................................................................... 28
3.11 RXMUTE (RECEIVER LOS WITH DATA MUTING, LINE SIDE ONLY) ...................................................... 29
F
IGURE
15. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
X
MUTE F
UNCTION
............................................................................................ 29
4.0 TRANSMIT PATH LINE INTERFACE ..................................................................................................30
F
IGURE
16. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
P
ATH
................................................................................................... 30
4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 31
F
IGURE
17. T
RANSMIT
D
ATA
S
AMPLED
ON
F
ALLING
E
DGE
OF
TCLK ............................................................................................... 31
F
IGURE
18. T
RANSMIT
D
ATA
S
AMPLED
ON
R
ISING
E
DGE
OF
TCLK ................................................................................................. 31
4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 32
4.3 JITTER ATTENUATOR (IF ENABLED IN THE TRANSMIT PATH) .............................................................. 32
4.4 TRANSMIT DIAGNOSTIC PATTERN GENERATION .................................................................................... 33
4.4.1 LINE SIDE AIS (TRANSMIT ALL ONES) ................................................................................................................... 33
F
IGURE
19. TAOS (T
RANSMIT
A
LL
O
NES
)...................................................................................................................................... 33
4.4.2 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 33
F
IGURE
20. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
ATAOS F
UNCTION
............................................................................................... 33
4.4.3 LINE SIDE PRBS/QRSS (PSEUDO/QUASI RANDOM BIT SEQUENCE)................................................................. 33
4.5 TRANSMIT DIAGNOSTIC PATTERN DETECTION ....................................................................................... 34
4.5.1 SLOS (SYSTEM LOSS OF SIGNAL).......................................................................................................................... 34
4.5.2 SYS_EXLOS (SYSTEM EXTENDED LOSS OF SIGNAL) ......................................................................................... 34
4.5.3 SAIS (SYSTEM ALARM INDICATION SIGNAL)........................................................................................................ 34
4.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 35
4.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 35
4.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 35
F
IGURE
21. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
.................................................................................................................. 35
4.6.3 SETTING REGISTERS TO SELECT AN ARIBTRARY PULSE................................................................................. 36
4.7 DMO (DIGITAL MONITOR OUTPUT, LINE SIDE ONLY) .............................................................................. 36
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83VSH316_07 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316ES 功能描述:外圍驅(qū)動器與原件 - PCI 16 CH T1/E1LIUSH LOW COST VERSION RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH316IB 功能描述:接口 - 專用 16 CH, SHRT HAUL T1/E1 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT83VSH316IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 16 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH316IB-F 制造商:Exar Corporation 功能描述:T1/E1 LIU IC
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