參數(shù)資料
型號： XRT83VSH316
廠商： Exar Corporation
英文描述： 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： 16-CHANNEL的T1/E1/J1短途線路接口單元
文件頁數(shù)： 5/96頁
文件大?。?/td> 600K
代理商： XRT83VSH316
PRELIMINARY
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316
II
REV. P1.0.3
4.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 37
F
IGURE
22. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
................................................................................... 37
5.0 T1/E1 APPLICATIONS ........................................................................................................................38
5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 38
5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 38
F
IGURE
23. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
L
OCAL
A
NALOG
L
OOPBACK
......................................................................................... 38
5.1.2 REMOTE LOOPBACK................................................................................................................................................ 39
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
R
EMOTE
L
OOPBACK
.................................................................................................... 39
5.1.3 DIGITAL LOOPBACK................................................................................................................................................. 40
F
IGURE
25. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
IGITAL
L
OOPBACK
..................................................................................................... 40
5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 41
F
IGURE
26. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
UAL
L
OOPBACK
........................................................................................................ 41
5.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 42
F
IGURE
27. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
AN
84-C
HANNEL
A
PPLICATION
..................................................................................... 42
5.3 LINE CARD REDUNDANCY .......................................................................................................................... 43
5.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS.................................................................................................... 43
5.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY.................................................................................. 43
F
IGURE
28. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
......................................... 43
5.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 44
F
IGURE
29. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
........................................... 44
5.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 44
5.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 45
F
IGURE
30. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
N+1 R
EDUNDANCY
...................................................... 45
5.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY................................................................................................... 46
F
IGURE
31. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
N+1 R
EDUNDANCY
........................................................ 46
5.4 POWER FAILURE PROTECTION .................................................................................................................. 47
5.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 47
5.6 NON-INTRUSIVE MONITORING .................................................................................................................... 47
F
IGURE
32. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
A
N
ON
-I
NTRUSIVE
M
ONITORING
A
PPLICATION
.............................................................. 47
5.7 ANALOG BOARD CONTINUITY CHECK ...................................................................................................... 48
F
IGURE
33. ATP
TESTING
BLOCK
DIAGRAM
..................................................................................................................................... 48
F
IGURE
34. T
IMING
D
IAGRAM
FOR
ATP T
ESTING
........................................................................................................................... 48
5.7.1 TRANSMITTER TTIP AND TRING TESTING............................................................................................................. 48
6.0 MICROPROCESSOR INTERFACE .....................................................................................................49
6.1 SPI SERIAL PERIPHERAL INTERFACE BLOCK ......................................................................................... 49
F
IGURE
35. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................. 49
6.1.1 SERIAL TIMING INFORMATION................................................................................................................................ 49
F
IGURE
36. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................................ 49
6.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION......................................................................................................... 50
6.1.3 ADDR[9:0] (SCLK1 - SCLK10)................................................................................................................................... 50
6.1.4 R/W (SCLK11)............................................................................................................................................................. 50
6.1.5 DUMMY BITS (SCLK12 - SCLK16)............................................................................................................................ 50
6.1.6 DATA[7:0] (SCLK17 - SCLK24)................................................................................................................................. 50
6.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 50
F
IGURE
37. T
IMING
D
IAGRAM
FOR
THE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................ 51
6.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 52
F
IGURE
38. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
.................................................................. 52
6.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 53
6.4 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .............................................................. 55
F
IGURE
39. I
NTEL
μP I
NTERFACE
T
IMING
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
W
HEN
ALE I
S
N
OT
T
IED
’HIGH’56
F
IGURE
40. I
NTEL
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
W
ITH
ALE=H
IGH
................. 57
6.5 MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ............................................................. 58
F
IGURE
41. M
OTOROLA
MPC86X μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.................... 59
F
IGURE
42. M
OTOROLA
68K μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
............................ 60
7.0 REGISTER DESCRIPTIONS ...............................................................................................................61
7.1 GLOBAL CONFIGURATION REGISTERS (0X000 - 0X00F) ......................................................................... 62
7.2 CHANNEL CONTROL REGISTERS (LINE AND SYSTEM SIDE) ................................................................. 63
7.3 OFFSET FOR PROGRAMMING THE CHANNEL NUMBER, N .................................................................... 63
7.4 GLOBAL CONTROL REGISTERS ................................................................................................................. 64
F
IGURE
43. R
EGISTER
0
X
0009
H
S
UB
R
EGISTERS
........................................................................................................................... 69
7.5 CONTROL AND LINE SIDE DIAGNOSTIC REGISTERS .............................................................................. 74
7.6 SYSTEM SIDE DIAGNOSTIC CHANNEL CONTROL REGISTERS .............................................................. 85
8.0 ELECTRICAL CHARACTERISTICS ...................................................................................................89
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83VSH316_07 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316ES 功能描述:外圍驅(qū)動器與原件 - PCI 16 CH T1/E1LIUSH LOW COST VERSION RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH316IB 功能描述:接口 - 專用 16 CH, SHRT HAUL T1/E1 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT83VSH316IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 16 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH316IB-F 制造商:Exar Corporation 功能描述:T1/E1 LIU IC
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