參數(shù)資料
型號(hào): XRT83VSH314
廠商: Exar Corporation
英文描述: 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 14-CHANNEL的T1/E1/J1短途線路接口單元
文件頁(yè)數(shù): 7/80頁(yè)
文件大?。?/td> 497K
代理商: XRT83VSH314
XRT83VSH314
4
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
1.0
PIN DESCRIPTIONS
MICROPROCESSOR
N
AME
P
IN
T
YPE
D
ESCRIPTION
CS
A22
I
Chip Select Input
Active low signal. This signal enables the microprocessor interface by pulling
chip select "Low". The microprocessor interface is disabled when the chip
select signal returns "High".
N
OTE
:
Internally pulled "High" with a 50k
resistor.
ALE_TS
C19
I
Address Latch Enable Input (Transfer Start)
See the Microprocessor section of this datasheet for a description.
N
OTE
:
Internally pulled "Low" with a 50k
resistor.
WR_R/W
A20
I
Write Strobe Input (Read/Write)
See the Microprocessor section of this datasheet for a description.
N
OTE
:
Internally pulled "Low" with a 50k
resistor.
RD_WE
D18
I
Read Strobe Input (Write Enable)
See the Microprocessor section of this datasheet for a description.
N
OTE
:
Internally pulled "Low" with a 50k
resistor.
RDY_TA
AA3
O
Ready Output (Transfer Acknowledge)
See the Microprocessor section of this datasheet for a description.
INT
B3
O
Interrupt Output
Active low signal. This signal is asserted "Low" when a change in alarm status
occurs. Once the status registers have been read, the interrupt pin will return
"High". GIE (Global Interrupt Enable) must be set "High" in the appropriate
global register to enable interrupt generation.
N
OTE
:
This pin is an open-drain output that requires an external 10K
pull-up
resistor.
μ
PCLK
AB2
I
Micro Processor Clock Input
In a synchronous microprocessor interface, μPCLK is used as the internal tim-
ing reference for programming the LIU.
N
OTE
:
Internally pulled "Low" with a 50k
resistor.
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XRT83VSH314IB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 14 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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