參數(shù)資料
型號(hào)： XRT83VSH314
廠商： Exar Corporation
英文描述： 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： 14-CHANNEL的T1/E1/J1短途線路接口單元
文件頁數(shù)： 4/80頁
文件大?。?/td> 497K
代理商： XRT83VSH314
XRT83VSH314
I
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
APPLICATIONS...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT83VSH314........................................................................................................................ 1
FEATURES
......................................................................................................................................................2
PRODUCT ORDERING INFORMATION..................................................................................................2
PIN OUT OF THE XRT83VSH314......................................................................................3
T
ABLE
OF
C
ONTENTS
............................................................................................................I
1.0 PIN DESCRIPTIONS ..............................................................................................................................4
M
ICROPROCESSOR
.........................................................................................................................................4
R
ECEIVER
S
ECTION
........................................................................................................................................6
T
RANSMITTER
S
ECTION
..................................................................................................................................9
C
ONTROL
F
UNCTION
....................................................................................................................................11
C
LOCK
S
ECTION
..........................................................................................................................................11
JTAG S
ECTION
............................................................................................................................................12
P
OWER
AND
G
ROUND
..................................................................................................................................13
N
O
C
ONNECTS
.............................................................................................................................................15
2.0 CLOCK SYNTHESIZER .......................................................................................................................16
T
ABLE
1: I
NPUT
C
LOCK
S
OURCE
S
ELECT
........................................................................................................................................ 16
F
IGURE
2. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
C
LOCK
S
YNTHESIZER
............................................................................................ 16
3.0 RECEIVE PATH LINE INTERFACE .....................................................................................................17
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
...................................................................................................... 17
3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 17
3.1.1 INTERNAL TERMINATION......................................................................................................................................... 17
T
ABLE
2: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
............................................................................................................................. 17
F
IGURE
4. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
.................................................................................... 17
T
ABLE
3: R
ECEIVE
T
ERMINATIONS
.................................................................................................................................................. 18
3.2 CLOCK AND DATA RECOVERY .................................................................................................................. 18
F
IGURE
5. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK .............................................................................................. 19
F
IGURE
6. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK............................................................................................ 19
T
ABLE
4: T
IMING
S
PECIFICATIONS
FOR
RCLK/RPOS/RNEG.......................................................................................................... 19
3.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 20
F
IGURE
7. T
EST
C
ONFIGURATION
FOR
M
EASURING
R
ECEIVE
S
ENSITIVITY
........................................................................................ 20
3.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 20
F
IGURE
8. T
EST
C
ONFIGURATION
FOR
M
EASURING
I
NTERFERENCE
M
ARGIN
.................................................................................... 20
3.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 21
F
IGURE
9. I
NTERRUPT
G
ENERATION
P
ROCESS
B
LOCK
..................................................................................................................... 21
3.2.4 FLSD (FIFO LIMIT STATUS DETECTION) ................................................................................................................ 22
3.3 JITTER ATTENUATOR ................................................................................................................................... 23
3.4 HDB3/B8ZS DECODER .................................................................................................................................. 23
F
IGURE
10. S
INGLE
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
................................................................................... 23
F
IGURE
11. D
UAL
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
...................................................................................... 23
3.5 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 24
F
IGURE
12. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
X
MUTE F
UNCTION
............................................................................................ 24
4.0 TRANSMIT PATH LINE INTERFACE ..................................................................................................25
F
IGURE
13. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
P
ATH
................................................................................................... 25
4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 25
F
IGURE
14. T
RANSMIT
D
ATA
S
AMPLED
ON
F
ALLING
E
DGE
OF
TCLK ............................................................................................... 25
F
IGURE
15. T
RANSMIT
D
ATA
S
AMPLED
ON
R
ISING
E
DGE
OF
TCLK ................................................................................................. 25
T
ABLE
5: T
IMING
S
PECIFICATIONS
FOR
TCLK/TPOS/TNEG ........................................................................................................... 26
4.2 HDB3/B8ZS ENCODER .................................................................................................................................. 26
T
ABLE
6: E
XAMPLES
OF
HDB3 E
NCODING
...................................................................................................................................... 26
T
ABLE
7: E
XAMPLES
OF
B8ZS E
NCODING
...................................................................................................................................... 26
4.3 JITTER ATTENUATOR ................................................................................................................................... 27
T
ABLE
8: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
.................................................................................... 27
4.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 27
F
IGURE
16. TAOS (T
RANSMIT
A
LL
O
NES
)...................................................................................................................................... 27
4.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 27
4.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 28
F
IGURE
17. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
ATAOS F
UNCTION
............................................................................................... 28
相關(guān)PDF資料
PDF描述
XRT83VSH314IB 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316 16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83VSH314ES 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 14 CHT1/E1LIUSH LOW COST VERSION RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH314IB 功能描述:接口 - 專用 14 CH, SH T1/E1 1.8V DGTL/3.3V ANLG RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT83VSH314IB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 14 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH314IB-SAM 制造商:Exar Corporation 功能描述:FOR FUJITSU ONLY
XRT83VSH316 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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