參數(shù)資料
型號: XRT83VSH314
廠商: Exar Corporation
英文描述: 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 14-CHANNEL的T1/E1/J1短途線路接口單元
文件頁數(shù): 61/80頁
文件大小: 497K
代理商: XRT83VSH314
XRT83VSH314
58
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
D1
RLOS
Receiver Loss of Signal
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = An RLOS condition is present
RO
0
D0
QRPD
Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0x04h and GIE is set to "1" in
the global register 0xE0h.
0 = No Alarm
1 = A QRP is detected
RO
0
T
ABLE
30: M
ICROPROCESSOR
R
EGISTER
0
X
06
H
B
IT
D
ESCRIPTION
C
HANNEL
0-13 (0
X
06
H
-0
X
D6
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Bit is Reserved
RUR
0
D6
DMOIS
Digital Monitor Output Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D5
FLSIS
FIFO Limit Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D4
LCV_OFIS
Line Code Violation / Overflow Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D3
Reserved
This Bit is Reserved
RUR
0
D2
AISDIS
Alarm Indication Signal Detection Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
N
OTE
:
The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
T
ABLE
29: M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
C
HANNEL
0-13 (0
X
05
H
-0
X
D5
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
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