參數(shù)資料
型號: XRT83SH38
廠商: Exar Corporation
英文描述: 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 8通道的T1/E1/J1短途線路接口單元
文件頁數(shù): 62/78頁
文件大?。?/td> 606K
代理商: XRT83SH38
XRT83SH38
59
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
D1
RLOS
Receiver Loss of Signal
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x04h and GIE is set to "1" in the global
register 0x80h.
0 = No Alarm
1 = An RLOS condition is present
RO
0
D0
QRPD
Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0x04h and GIE is set to "1" in
the global register 0x80h.
0 = No Alarm
1 = A QRP is detected
RO
0
T
ABLE
29: M
ICROPROCESSOR
R
EGISTER
0
X
06
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7 (0
X
06
H
-0
X
76
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used.
D6
DMOIS
Digital Monitor Output Status
0 = No change
1 = Change in status occurred
RUR
0
D5
FLSIS
FIFO Limit Status
0 = No change
1 = Change in status occurred
RUR
0
D4
LCV/OFIS
Line Code Violation / Overflow Status
0 = No change
1 = Change in status occurred
RUR
0
D3
Reserved
This Register Bit is Not Used.
D2
AISDIS
Alarm Indication Signal Status
0 = No change
1 = Change in status occurred
RUR
0
N
OTE
:
The GIE bit in the global register 0x80h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
T
ABLE
28: M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
C
HANNEL
0-7 (0
X
05
H
-0
X
75
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
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