參數(shù)資料
型號： XRT83SH38
廠商： Exar Corporation
英文描述： 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： 8通道的T1/E1/J1短途線路接口單元
文件頁數(shù)： 5/78頁
文件大?。?/td> 606K
代理商： XRT83SH38
XRT83SH38
I
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
A
PPLICATIONS
............................................................................................................................................................... 1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT83SH38 T1/E1/J1 LIU (H
OST
M
ODE
)....................................................................................... 1
F
IGURE
2. B
LOCK
D
IAGRAM
OF
THE
XRT83SH38 T1/E1/J1 LIU (H
ARDWARE
M
ODE
).............................................................................. 2
F
EATURES
..................................................................................................................................................................... 3
ORDERING INFORMATION ....................................................................................................................3
PIN DESCRIPTION BY FUNCTION............................................................................................... 5
R
ECEIVE
S
ECTION
......................................................................................................................................................... 5
T
RANSMIT
S
ECTION
....................................................................................................................................................... 8
M
ICROPROCESSOR
I
NTERFACE
.................................................................................................................................... 10
JITTER
A
TTENUATOR
.................................................................................................................................................... 12
C
LOCK
S
YNTHESIZER
.................................................................................................................................................. 12
A
LARM
F
UNCTIONS
/R
EDUNDANCY
S
UPPORT
................................................................................................................. 14
S
ERIAL
P
ORT
AND
JTAG
............................................................................................................................................... 16
P
OWER
AND
G
ROUND
.................................................................................................................................................. 17
FUNCTIONAL DESCRIPTION...................................................................................................... 19
1.0 HARDWARE MODE VS HOST MODE ................................................................................................19
1.1 FEATURE DIFFERENCES IN HARDWARE MODE ...................................................................................... 19
T
ABLE
1: D
IFFERENCES
B
ETWEEN
H
ARDWARE
M
ODE
AND
H
OST
M
ODE
................................................................................................. 19
2.0 MASTER CLOCK GENERATOR .........................................................................................................20
F
IGURE
3. T
WO
I
NPUT
C
LOCK
S
OURCE
................................................................................................................................................. 20
F
IGURE
4. O
NE
I
NPUT
C
LOCK
S
OURCE
................................................................................................................................................. 20
T
ABLE
2: M
ASTER
C
LOCK
G
ENERATOR
................................................................................................................................................. 20
3.0 RECEIVE PATH LINE INTERFACE ....................................................................................................21
F
IGURE
5. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
............................................................................................................ 21
3.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 21
3.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 21
T
ABLE
3: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
................................................................................................................................... 21
F
IGURE
6. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
.......................................................................................... 22
3.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 22
T
ABLE
4: S
ELECTING
THE
V
ALUE
OF
THE
E
XTERNAL
F
IXED
R
ESISTOR
.................................................................................................... 22
F
IGURE
7. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
O
NE
E
XTERNAL
F
IXED
R
ESISTOR
............................................................................. 22
3.2 CLOCK AND DATA RECOVERY ................................................................................................................... 22
F
IGURE
8. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK..................................................................................................... 23
F
IGURE
9. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK................................................................................................... 23
T
ABLE
5: T
IMING
S
PECIFICATIONS
FOR
RCLK/RPOS/RNEG ................................................................................................................ 23
3.2.1 RECEIVE SENSITIVITY.............................................................................................................................................. 23
F
IGURE
10. T
EST
C
ONFIGURATION
FOR
M
EASURING
R
ECEIVE
S
ENSITIVITY
............................................................................................ 24
3.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 24
F
IGURE
11. T
EST
C
ONFIGURATION
FOR
M
EASURING
I
NTERFERENCE
M
ARGIN
......................................................................................... 24
3.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION........................................................................ 24
3.2.3.1 RLOS (R
ECEIVER
L
OSS
OF
S
IGNAL
) ..................................................................................................................... 24
F
IGURE
12. A
NALOG
R
ECEIVE
L
OS
OF
S
IGNAL
FOR
T1/E1/J1................................................................................................................ 25
T
ABLE
6: A
NALOG
RLOS D
ECLARE
/C
LEAR
(T
YPICAL
V
ALUES
)
FOR
T1/E1............................................................................................. 25
3.2.3.2 EXLOS (E
XTENDED
L
OSS
OF
S
IGNAL
) ................................................................................................................. 25
3.2.3.3 AIS (A
LARM
I
NDICATION
S
IGNAL
) ......................................................................................................................... 25
3.2.3.4 FLSD (FIFO L
IMIT
S
TATUS
D
ETECTION
) ............................................................................................................... 25
3.2.3.5 LCVD (L
INE
C
ODE
V
IOLATION
D
ETECTION
) ........................................................................................................... 25
3.3 RECEIVE JITTER ATTENUATOR .................................................................................................................. 26
3.4 HDB3/B8ZS DECODER .................................................................................................................................. 26
3.5 RPOS/RNEG/RCLK ........................................................................................................................................ 26
F
IGURE
13. S
INGLE
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
......................................................................................... 26
F
IGURE
14. D
UAL
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
............................................................................................ 26
3.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 27
F
IGURE
15. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
X
MUTE F
UNCTION
................................................................................................... 27
4.0 TRANSMIT PATH LINE INTERFACE .................................................................................................28
F
IGURE
16. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
P
ATH
......................................................................................................... 28
4.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 28
F
IGURE
17. T
RANSMIT
D
ATA
S
AMPLED
ON
F
ALLING
E
DGE
OF
TCLK...................................................................................................... 28
F
IGURE
18. T
RANSMIT
D
ATA
S
AMPLED
ON
R
ISING
E
DGE
OF
TCLK........................................................................................................ 28
相關(guān)PDF資料
PDF描述
XRT83SH38_0609 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH38IB 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL216 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL216_06 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL216IB 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83SH38_0609 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH38ES 功能描述:外圍驅(qū)動器與原件 - PCI 8 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SH38IB 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SH38IB-F 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SL216 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
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