參數(shù)資料
型號: XRT83SH38
廠商: Exar Corporation
英文描述: 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 8通道的T1/E1/J1短途線路接口單元
文件頁數(shù): 26/78頁
文件大?。?/td> 606K
代理商: XRT83SH38
XRT83SH38
23
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To
update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register.
Figure 8
is a
timing diagram of the receive data updated on the rising edge of RCLK.
Figure 9
is a timing diagram of the
receive data updated on the falling edge of RCLK. The timing specifications are shown in
Table 5
.
F
IGURE
8. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK
F
IGURE
9. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK
N
OTE
:
VDD=3.3V ±5%, T
A
=25°C, Unless Otherwise Specified
3.2.1
Receive Sensitivity
To meet short haul requirements, the XRT83SH38 can accept T1/E1/J1 signals that have been attenuated by
12dB of flat loss in E1 mode or by 655 feet of cable loss along with 6dB of flat loss in T1 mode. However, the
XRT83SH38 can tolerate cable loss and flat loss beyond the industry specifications. The receive sensitivity in
the short haul mode is approximately 4,000 feet without experiencing bit errors, LOF, pattern synchronization,
etc. Although data integrity is maintained, the RLOS function (if enabled) will report an RLOS condition
T
ABLE
5: T
IMING
S
PECIFICATIONS
FOR
RCLK/RPOS/RNEG
P
ARAMETER
S
YMBOL
M
IN
T
YP
M
AX
U
NITS
RCLK Duty Cycle
R
CDU
45
50
55
%
Receive Data Setup Time
R
SU
150
-
-
ns
Receive Data Hold Time
R
HO
150
-
-
ns
RCLK to Data Delay
R
DY
-
-
40
ns
RCLK Rise Time (10% to 90%)
with 25pF Loading
RCLK
R
-
-
40
ns
RCLK Fall Time (90% to 10%)
with 25pF Loading
RCLK
F
-
-
40
ns
RCLK
RPOS
or
RNEG
R
DY
RCLK
R
RCLK
F
R
OH
RCLK
RPOS
or
RNEG
R
DY
RCLK
F
RCLK
R
R
OH
相關(guān)PDF資料
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