參數(shù)資料
型號: XRT83SH38
廠商: Exar Corporation
英文描述: 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 8通道的T1/E1/J1短途線路接口單元
文件頁數(shù): 33/78頁
文件大?。?/td> 606K
代理商: XRT83SH38
XRT83SH38
30
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
4.3
Transmit Jitter Attenuator
The XRT83SH38 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are typically
removed which can leave gaps in the incoming data stream. The transmit path has a dedicated jitter
attenuator with a 32-Bit or 64-Bit FIFO that is used to smooth the gapped clock into a steady T1 or E1 output.
The maximum gap width of the 8-Channel LIU is shown in
Table 10
.
N
OTE
:
If the LIU is used in a loop timing system, the receive path has a dedicated jitter attenuator. See the Receive
Section of this datasheet.
4.4
TAOS (Transmit All Ones)
The XRT83SH38 has the ability to transmit all ones on a per channel basis by programming the appropriate
channel register. This function takes priority over the digital data present on the TPOS/TNEG inputs. For
example: If a fixed "0011" pattern is present on TPOS in single rail mode and TAOS is enabled, the transmitter
will output all ones. In addition, if digital or dual loopback is selected, the data on the RPOS output will be
equal to the data on the TPOS input.
Figure 19
is a diagram showing the all ones signal at TTIP and TRING.
F
IGURE
19. TAOS (T
RANSMIT
A
LL
O
NES
)
4.5
Transmit Diagnostic Features
In addition to TAOS, the XRT83SH38 offers diagnostic features for analyzing network integrity such as ATAOS
and QRSS on a per channel basis by programming the appropriate registers. These diagnostic features take
priority over the digital data present on TPOS/TNEG inputs. The transmitters will send the diagnostic code to
the line and will be maintained in the digital loopback if selected. When the LIU is responsible for sending
diagnostic patterns, the LIU is automatically placed in the single rail mode.
T
ABLE
10: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
FIFO D
EPTH
M
AXIMUM
G
AP
W
IDTH
32-Bit
20 UI
64-Bit
50 UI
TAOS
1
1
1
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