- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1977 > XRT81L27IV-F (Exar Corporation)IC LIU EI 7CH 3.3V 128TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT81L27IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 29/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU EI 7CH 3.3V 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 應(yīng)用： | DECT |
| 接口： | 串行 |
| 電源電壓： | 3.3V |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁
XRT81L27
á
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
6
52
TNEG_5/
CODE_5
I-L
Transmitter 5 Negative Data Input: (see pin 39)I
53
TPOS_5/
TDATA_5
I
Transmitter 5 Positive/ NRZ Data Input: (see pin 38)
54
TClk_5
I
Transmitter 5 Clock Input: E1 rate at 2.048MHz ± 50ppm.
55
GND
Gnd
Digital Supply Ground
56
VDD
Vdd
Digital Positive Supply(3.3V± 5%)
57
LOS_5
O
Receiver 5 Loss of Signal: (see pin 2)
58
RPOS_5/
RDATA_5
O
Receiver 5 Positive/NRZ Data Output: (see pin 35)
59
RNEG_5/
LCV_5
O
Receiver 5 Negative Data Output: (see pin 34)
60
RClk_5
O
Receiver 5 Clock Output.
61
LOS_6
O
Receiver 6 Loss of Signal: (see pin 2)
62
RPOS_6/
RDATA_6
O
Receiver 6 Positive /NRZ Data Output: (see pin 35)
63
RNEG_6/
LCV_6
O
Receiver 6 Negative Data Output: (see pin 34)
64
RClk_6
O
Receiver 6 Clock Output.
65
RClkP
I-L
Receiver Clock Output Polarity: (Hardware Mode)
"Low", All channel RPOS /RDATA and RNEG/LCV output data are
updated on the falling edge of RClk.
"High" to select data update on rising edge of RClk.
66
TClkP
I-L
Transmit Clock Polarity: (Hardware Mode)
"Low", transmit input data is sampled using the falling edge of TClk.
"High" to select rising edge of TClk for data sampling.
67
RRING_6
I
Receiver 6 Bipolar Negative Input:
68
RTIP_6
I
Receiver 6 Bipolar Positive Input:
69
SR/DR
I-L
Single-rail/Dual-rail Select:
In Hardware Mode and with this pin tied to "High", input transmit data
and receive output data is selected for Single-Rail mode operation.
"Low" to select Dual-Rail mode.
70
MClk
I
Master Clock Input:
This signal is an independent 2.048MHz clock with accuracy better than
±50ppm and duty cycle within 40% to 60%. The function of MCLK is to
provide timing source for the PLL clock recovery circuit, reference clock
to insert All Ones data in the transmit as well as the receive paths.
71
TGND_5
Gnd
Transmitter 5 Supply Ground
72
TRING_5
O
Transmitter 5 Ring Output: Negative bipolar data output to the line
PIN DESCRIPTIONS
NOTE: I -H indicates an input pin with a 50k
pull-up Resistor, I-L indicates an input pin with a 50k pull-down resistor.
PIN #NAME
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT82D20IW-F | IC LIU E1 SGL 28SOJ |
| XRT82L24AIV-F | IC LIU E1 QAUD 100TQFP |
| XRT83D10IW | IC LIU T1/E1 SGL 28SOJ |
| XRT83L30IV-F | IC LIU LH/SH T1/E1 SGL 64TQFP |
| XRT83L314IB-L | IC LIU T1/E1/J1 14CH 304TBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR-T8205CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telephone Ringer |
| XR-T8205P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telephone Ringer |
| XRT82D20 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL E1 LINE INTERFACE UNIT |
| XRT82D20_06 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL E1 LINE INTERFACE UNIT |
| XRT82D20ES | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 1 CH E1 LIU RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。