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參數(shù)資料
| 型號： | XRT81L27IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 16/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU EI 7CH 3.3V 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 應(yīng)用： | DECT |
| 接口： | 串行 |
| 電源電壓： | 3.3V |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
21
2.3.1
Timing Control Block
The Timing Control block contains several sub-
blocks. These functions are used to control the timing
on the input data stream such that the output meets
all system timing specifications.
2.3.2
The Transmit Clock Duty Cycle Adjust Cir-
cuit
The on-chip Pulse-Shaping circuitry in the Transmit
Section of the XRT81L27 has the responsibility for
generating pulses of the shape and width to comply
with the applicable pulse template requirement. The
widths of these output pulses are defined by the width
of the half-period pulses in the TCLK signal.
Allowing the widths of the pulses in the TCLK clock
signal to vary significantly could jeopardize the chip’s
ability to generate Transmit Output pulses of the ap-
propriate width, thereby failing the applicable Pulse
Template Requirement Specification. The chips ability
to generate compliant pulses could depend upon the
duty cycle of the clock signal applied to the TCLK in-
put pin.
In order to combat this phenomenon, the Transmit
Clock Duty Cycle Adjust circuit was designed into the
XRT81L27. The Transmit Clock Duty Cycle Adjust
Circuitry is a PLL that was designed to accept clock
pulses via the TCLK input pin at duty cycles ranging
from 30% to 70% and to regenerate these signals
with a 50% duty cycle.
The XRT81L27 Transmit Clock Duty Cycle Adjust cir-
cuit alleviates the need to supply a signal with a 50%
duty cycle to the TCLK input pin.
2.3.3
Transmit All Ones
In some conditions the system will control the chip
such that it will transmit “all ones” data onto the line. It
is possible that a valid TClk is not available and so the
MClk signal will be used to provide the timing. It
should be noted that the Local feedback will NOT in-
clude the “all ones” bit stream so this data is diverted
before going into the pulse shaper circuit.
2.4
THE PULSE SHAPING CIRCUIT
The purpose of the "Transmit Pulse Shaping" Circuit
is to generate Transmit Output pulses that comply
with the ITU-T G.703 Pulse Template Requirements
for E1 applications, even with TClk duty cycle be-
tween 30 and 70%.
As a consequence, each channel (within the
XRT81L27) will take each mark which is provided to it
via the Transmit Input Interface block, and will gener-
ate a pulse that complies with the pulse template,
presented in Figure 11, (when measured on the sec-
ondary-side of the Transmit Output Transformer).
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