THE
參數(shù)資料
型號(hào)： XRT81L27IV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 21/30頁(yè)
文件大?。?/td> 0K
描述： IC LIU EI 7CH 3.3V 128TQFP
標(biāo)準(zhǔn)包裝： 72
應(yīng)用： DECT
接口： 串行
電源電壓： 3.3V
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 托盤(pán)
安裝類型： 表面貼裝
XRT81L27
á
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
26
3.4
THE PEAK DETECTOR AND SLICER BLOCK
After the incoming line signal has passed through the
Receive Equalizer block, it will next be routed to the
Slicer block. The purpose of the Slicer block is to
quantify a given bit-period (or symbol) within the in-
coming line signal as either a “1” or a “0”.
3.5
THE LOS DETECTOR BLOCK
The LOS Detector block, within each channel (of the
XRT81L27) was specifically designed to comply with
the LOS Declaration/Clearance requirements per
ITU-T G.775. As a consequence, the channel will de-
clare an LOS Condition, (by driving the LOS output
pin “High”) if the received line signal amplitude drops
to –20dB or below. Further, the channel will clear the
LOS Condition if the signal amplitude rises back up to
–15dB typically, or above. The XRT81L27 was de-
signed to meet the ITU-T G.775 specification timing
requirements for declaring and clearing the LOS indi-
cator. In particular, the XRT81L27 will declare an LOS
between 10 and 255 UI (or E1 bit periods) after the
actual time the LOS condition occurred. Further, the
XRT81L27 will clear the LOS indicator within 10 to
255 UI after restoration of the incoming line signal.
When operating in the Host mode, the LOS time can
be extended to 4096 zeros by the activation of the
EXLOS bit in the Command Control Register. This
will provide for those cases where the G.775 specifi-
cation value is not long enough,
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