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參數(shù)資料
| 型號： | XRT73L03BIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 61/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| 標準包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應商設備封裝： | 120-LQFP（14x20） |
| 包裝： | 托盤 |
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XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
7
96
REGR/
RxClkINV
I
Register Reset Input (Invert RxClk(n)) Output - Select:
The function of this pin depends upon whether the XRT73L03B is oper-
ating in the HOST Mode or in the Hardware Mode.
NOTE: This pin is internally pulled "High".
In the HOST-Mode - Register Reset Input:
Setting this input pin "Low" causes the XRT73L03B to reset the contents
of the Command Registers to their default settings and default operating
configuration.
In the Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Section of all Chan-
nels in the XRT73L03B to invert their RxClk_(n) clock output signals and
configures Channel (n) to output the recovered data via the RPOS_(n)
and RNEG_(n) output pins on the falling edge of RxClk_(n).
Setting this pin "Low" configures Channel (n) to output the recovered
data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of
RxClk_(n).
RECEIVE INTERFACE
PIN #NAME
TYPE
DESCRIPTION
CLOCK INTERFACE
PIN #NAME
TYPE
DESCRIPTION
47
99
103
EXClk_0
EXClk_1
EXClk_2
I
External Reference Clock Input - Channel (n):
Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz
clock signal for DS3 applications or a 51.84 MHz clock signal for SONET
STS-1 applications.
The Channel (n) Clock Recovery PLL uses this signal as a Reference
Signal for Declaring and Clearing the Receive Loss of Lock Alarm. The
Clock recovery PLL also generates the exact clock for the LIU.
It is permissible to use the same clock that drives the TxClk_(n) input
pin.
It is permissible to operate the three Channels at different data rates.
OPERATING MODE SELECT
PIN #NAME
TYPE
DESCRIPTION
93
SR/(DR)I
Receive Output Single-Rail/Dual-Rail Select:
Setting this pin "High" configures the Receive Sections of all Channels to
output data in a Single-Rail Mode to the Terminal Equipment.
Setting this pin "Low" configures the Receive Section of all Channels to
output data in a Dual-Rail Mode to the Terminal Equipment.
相關PDF資料 |
PDF描述 |
|---|---|
| XRT73L04BIV-F | IC LIU E3/DS3/STS-1 4CH 144LQFP |
| XRT73L06IB-F | IC LIU E3/DS3/STS-1 6CH 217BGA |
| XRT73LC00AIV-F | IC LIU STS1/DS3/E3 SGL 44TQFP |
| XRT73LC03AIV-F | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| XRT73LC04AIV-F | IC LIU E3/DS3/STS-1 4CH 144LQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L03IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
| XRT73L03IVS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT73L04A | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04B | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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