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參數(shù)資料
| 型號： | XRT73L03BIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 25/61頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 3/3 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP（14x20） |
| 包裝： | 托盤 |
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XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
29
2. If the Transmit Section of a given channel is config-
ured to accept Single-Rail data from the Terminal
Equipment, the B3ZS/HDB3 Encoder must be
enabled.
Figure 16 illustrates the behavior of the TPData_(n)
and TxClk_(n) signals when the Transmit Logic Block
has been configured to accept Single-Rail data from
the Terminal Equipment.
2.2
THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR-
CUITRY
The on-chip Pulse-Shaping circuitry within the Trans-
mit Section of each Channel in the XRT73L03B gen-
erates pulses of the appropriate shapes and width to
meet the applicable pulse template requirements.
The widths of these output pulses are defined by the
width of the half-period pulses within the TxClk_(n)
signal.
However, if the widths of the pulses within the
TxClk_(n) clock signal are allowed to vary significant-
ly, this could jeopardize the chip’s ability to generate
Transmit Output pulses of the appropriate width and
thereby not meet the Pulse Template requirement
specification. Consequently, the chip’s ability to gen-
erate compliant pulses could depend upon the duty
cycle of the clock signal applied to the TxClk_(n) input
pin.
The Transmit Clock Duty Cycle Adjust Circuitry ac-
cepts clock pulses via the TxClk_(n) input pin at duty
cycles ranging from 30% to 70% and converts them
to a 50% duty cycle.
2.3
THE HDB3/B3ZS ENCODER BLOCK
The purpose of the HDB3/B3ZS Encoder Block is to
aid in the Clock Recovery process at the Remote Ter-
minal Equipment by ensuring an upper limit on the
number of consecutive zeros that can exist within the
line signal.
2.3.1
B3ZS Encoding
If the XRT73L03B has been configured to operate in
the DS3 or SONET STS-1 Modes, then the HDB3/
B3ZS Encoder blocks operate in the B3ZS Mode.
When the Encoder is operating in this mode, it parses
through and searches the Transmit Binary Data
Stream from the Transmit Logic Block for the occur-
rence of three (3) consecutive zeros (e.g., "000"). If
the B3ZS Encoder finds an occurrence of three con-
secutive zeros, then it substitutes these three "0’s",
with either a "00V" or a "B0V" pattern.
Where:
"B" represents a Bipolar pulse that is compliant with
the Alternating Polarity requirements of the AMI (Al-
ternate Mark Inversion) line code; and
"V" represents a Bipolar Violation (e.g., a bipolar
pulse that violates the Alternating Polarity require-
ments of the AMI line code).
The B3ZS Encoder decides whether to substitute
with either the “00V" or the "B0V" pattern in order to
insure that an odd number of bipolar pulses exist be-
tween any two consecutive violation pulses.
Figure 17 illustrates the B3ZS Encoder at work with
two separate strings of three (or more) consecutive
zeros
FIGURE 16. THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SGNALS, WHILE THE TRANSMIT LOGIC BLOCK IS
ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT
TxClk
TPData
Data
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73L04BIV-F | IC LIU E3/DS3/STS-1 4CH 144LQFP |
| XRT73L06IB-F | IC LIU E3/DS3/STS-1 6CH 217BGA |
| XRT73LC00AIV-F | IC LIU STS1/DS3/E3 SGL 44TQFP |
| XRT73LC03AIV-F | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| XRT73LC04AIV-F | IC LIU E3/DS3/STS-1 4CH 144LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L03IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
| XRT73L03IVS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT73L04A | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04B | 制造商:EXAR 制造商全稱:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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