Preliminary Figure 17. Pixel Rate Clock Timing with RSTreject=1 CCD Signal SBLK SPIX ADCLK Reset Reject Switches Turn OF" />
參數(shù)資料
型號(hào)： XRD98L62ACV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 21/37頁(yè)
文件大?。?/td> 0K
描述： IC CCD DIGITIZER 12BIT 48TQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 12
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤(pán)
XRD98L62
28
Rev. P2.00
Preliminary
Figure 17. Pixel Rate Clock Timing with RSTreject=1
CCD Signal
SBLK
SPIX
ADCLK
Reset Reject
Switches Turn OFF
Video
Level
φ3
Black
Level
Aperture delays
One of the most difficult tasks in designing a digital
camera is optimizing the pixel timing for the CCD, CDS
and ADC. We have included the programmable aper-
ture delay function to help simplify this job.
There are two serial interface registers, DelayA &
DelayB, used to program the aperture delays. Each
register is divided into 3 delay parameters. Each delay
parameter is 3 bits wide. Each delay parameter can be
set to add from 0ns to 7ns of delay.
The delays are added to the clock signals after the
polarity control. This means the definition of leading
edge and trailing edge depends on the polarity control
bit for each clock. For the default case, SBLKpol=0 &
SPIXpol=0, the leading edge is the falling edge and the
trailing edge is the rising edge.
DelayA[2:0] controls the delay added to the leading
edge of SBLK.
This positions the falling edge of
internal signal
φ1.
DelayA[5:3] controls the delay added to the trailing
edge of SBLK. This positions the rising edge of
internal signal
φ1.
DelayB[2:0] controls the delay added to the leading
edge of
φ2. This positions the falling edge of internal
signal
φ2.
DelayB[5:3] controls the delay added to the trailing
edge of SPIX. This positions the rising edge of
internal signal
φ2.
DelayB[8:6] is only used when SPIXopt=0. It controls
the delay from the trailing edge of SBLK to the start
of the internal
φ2 control. This delay is in addition to
DelayA[5:3], the SBLK trailing edge delay.
DelayA[8:6] controls the delay added to ADCLK. This
is a simple delay, it adds the same delay to both the
rising and falling edges of ADCLK to create
φ4.
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XRD98L62EVAL 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 XRD98L62 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
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XRD98L63AIV-F 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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