Preliminary Direct PGA Input Mode The inputs to the PGA can be accessed directly (bypassing the CDS) through the Test1 &" />
參數(shù)資料
型號： XRD98L62ACV-F
廠商： Exar Corporation
文件頁數(shù)： 11/37頁
文件大小： 0K
描述： IC CCD DIGITIZER 12BIT 48TQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 12
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
19
Rev. P2.00
XRD98L62
Preliminary
Direct PGA Input Mode
The inputs to the PGA can be accessed directly
(bypassing the CDS) through the Test1 & Test2 pins.
This mode is very useful for testing the PGA gain and
linearity. To enable the Direct PGA Input mode, write
a “1” to the NoCDS bit in the Control register of the
serial interface. This will disconnect the CDS from the
PGA input and turn on the switches that connect the
Test1 & Test2 pins to the PGA.
In this mode the SBLK and SPIX clocks must be
clocked, due to the switched capacitor architecture of
the second PGA stage. ADCLK must be provided to
digitize the PGA output. The analog PGA output
cannot be monitored, it does not come out to any pin.
The calibration logic should be put into the Hold mode,
or into the ManCAL mode. The Coarse offset correc-
tion DAC does not affect the Direct PGA inputs, but the
Fine offset correction DAC does affect the PGA out-
put. The calibration logic is not “aware” that the Coarse
DAC is not active, and thus could cause errors if left
operating automatically.
Figure 7. Direct PGA Input Timing
Input Signal
Test1-Test2
SPIX
ADCLK
Input Sampled
PGA tracks
Input Signal
ADC tracks
PGA output
Input Sampled
SBLK
non-overlap
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XRD98L62EVAL 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 XRD98L62 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
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