Preliminary Reset Reject In the default state the reset reject switches ( φ3)are always ON, they are not clocked. The re" />
參數(shù)資料
型號: XRD98L62ACV-F
廠商: Exar Corporation
文件頁數(shù): 20/37頁
文件大?。?/td> 0K
描述: IC CCD DIGITIZER 12BIT 48TQFP
標準包裝: 250
位數(shù): 12
通道數(shù): 1
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 2.7 V ~ 3.6 V
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
27
Rev. P2.00
XRD98L62
Preliminary
Reset Reject
In the default state the reset reject switches (
φ3)are
always ON, they are not clocked. The reset pulse of
each pixel is transmitted to the first stage of the PGA.
Depending on the PGA gain and the actual voltage
level of the reset pulse, this could cause the first stage
of the PGA to rail. During the Black Level sampling the
PGA should have enough time to recuperate, but as a
precaution we have included the Reset Reject option.
When RSTreject = 1, the reset reject switches are
turned OFF at the end of the SPIX pulse, and turned
ON again at the start of the SBLK pulse. This will
effectively reject the reset pulse and prevent it from
railing the PGA.
CCD Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
φ2
DelayB[8:6]
Figure 15. Pixel Rate Clock Timing with SPIXopt=0 (Default)
CCD Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
φ2
Figure 16. Pixel Rate Clock Timing with SPIXopt=1
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