REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO INTA (IRQ#) 22 30 D6 O When 16/68# pin is HIGH for Intel bus interface," />
參數(shù)資料
型號： XR68M752IM48-F
廠商： Exar Corporation
文件頁數(shù)： 45/54頁
文件大?。?/td> 0K
描述： IC UART FIFO 64B DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1479
1016-1479-ND
1016-1642
XR68M752IM48-F-ND
XR16M752/XR68M752
5
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
INTA
(IRQ#)
22
30
D6
O
When 16/68# pin is HIGH for Intel bus interface, this out-
put becomes channel A interrupt output. The output state
is defined by the user through the software setting of
MCR[3]. INTA is set to the active mode and OP2A# out-
put LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# to HIGH when MCR[3]
is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this
output becomes device interrupt output (active low, open
drain). An external pull-up resistor is required for proper
operation.
INTB
(NC)
21
29
D7
O
When 16/68# pin is HIGH for Intel bus interface, this out-
put becomes channel B interrupt output. The output state
is defined by the user through the software setting of
MCR[3]. INTB is set to the active mode and OP2A# out-
put to LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# to HIGH when MCR[3]
is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this
output is not used.
TXRDYA#
-
43
C4
O
UART channel A Transmitter Ready (active low). The
output provides the TX FIFO/THR status for transmit
channel A. See
Table 3. If it is not used, leave it uncon-
nected.
RXRDYA#
-
31
E5
O
UART channel A Receiver Ready (active low). This out-
put provides the RX FIFO/RHR status for receive channel
A. See
Table 3. If it is not used, leave it unconnected.
TXRDYB#
-
6
D4
O
UART channel B Transmitter Ready (active low). The
output provides the TX FIFO/THR status for transmit
channel B. See
Table 4. If it is not used, leave it uncon-
nected.
RXRDYB#
-
18
F4
O
UART channel B Receiver Ready (active low). This out-
put provides the RX FIFO/RHR status for receive channel
B. See
Table 3. If it is not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
5
7
D3
O
UART channel A Transmit Data or infrared encoder data.
Standard transmit and receive interface is enabled when
MCR[6] = 0. In this mode, the TX signal will be HIGH dur-
ing reset or idle (no data). Infrared IrDA transmit and
receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is LOW. If it is not used, leave
it unconnected.
Pin Description
NAME
32-QFN
PIN #
48-TQFP
PIN #
49-STBGA
PIN #
TYPE
DESCRIPTION
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