- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3766 > XR68M752IM48-F (Exar Corporation)IC UART FIFO 64B DUAL 48TQFP PDF資料下載
參數(shù)資料
| 型號： | XR68M752IM48-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 10/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 64B DUAL 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232，RS422，RS485 |
| 電源電壓： | 1.62 V ~ 3.63 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1479 1016-1479-ND 1016-1642 XR68M752IM48-F-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Error
Ta
gs
(64
-s
et
s)
Err
or
Tag
sin
LS
R
b
its
4:
2
Receive Data Characters
FIFO
Trigger=16
Example
: - RX FIFO trigger level selected at 16 bytes
(See Note Below)
Data fills to
Halt Level
Data falls to
Resume Level
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills to the Halt Level
to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls to the Resume
Level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
64 bytes by 11-bit wide
FIFO
XR16M752/XR68M752
18
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
2.11
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 11):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.12
Auto RTS Halt and Resume
The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches the Halt Level (TCR[3:0]). The
RTS# pin will return LOW after the RX FIFO is unloaded to the Resume Level (TCR[7:4]). Under these
conditions, the M752 will continue to accept data if the remote UART continues to transmit data. It is the
responsibility of the user to ensure that the Halt Level is greater than the Resume Level. If interrupts are used,
it is recommended that Halt Level > RX Trigger Level > Resume Level. The Auto RTS function is initiated
when the RTS# output pin is asserted LOW (RTS On).
2.13
Auto RS485 Half-duplex Control
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by DLD
bit-6. When idle, the auto RS485 half-duplex direction control signal (RTS#) is LOW for receive mode. When
data is loaded into the THR for transmission, the RTS# output is automatically asserted HIGH prior to sending
the data. After the last stop bit of the last character that has been transmitted, the RTS# signal is automatically
de-asserted. This helps in turning around the transceiver to receive the remote station’s response. When the
host is ready to transmit next polling data packet, it only has to load data bytes to the transmit FIFO. The
transmitter automatically re-asserts RTS# (HIGH) output prior to sending the data. In addition to changing the
behavior of the RTS# output, this feature also changes the behavior of the transmit empty interrupt (see
Table 4). In the 49-pin STBGA package, this feature can be enabled by connecting the EN485# pin to GND. If
this feature is enabled by the EN485# pin, it can be disabled by DLD bit-6 after power-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16M752IM48-F | IC UART FIFO 34B DUAL 48TQFP |
| ST16C450CQ48-F | IC UART SINGLE 48TQFP |
| ST16C2450IQ48-F | IC UART FIFO DUAL 48TQFP |
| MAX7314AEG+T | IC I/O EXPANDER I2C 16B 24QSOP |
| ST16C550IQ48-F | IC UART FIFO 16B SGL 48TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR68M752IM48TR-F | 制造商:Exar Corporation 功能描述:XR68M752 Series 16 Mbps High Performance DUART With 64-Byte FIFO - TQFP-48 |
| XR7090AA-BC-0001 | 制造商:CREE 制造商全稱:Cree, Inc 功能描述:XLamp㈢ XR LED Binning and Labeling |
| XR7090AA-BC-DD-EF-G-HHHH | 制造商:CREE 制造商全稱:Cree, Inc 功能描述:XLamp㈢ XR LED Binning and Labeling |
| XR7090-AM-L1-0001 | 制造商:Cree 功能描述:LED AMBER XR 制造商:Cree 功能描述:LED, AMBER, XR 制造商:Cree 功能描述:LED, HIGH BRIGHTNESS, RED ORANGE, 67.2LM; Series:XLamp XR; LED Color:Amber; Luminous Flux @ Test:42lm; Wavelength Typ:595nm; Forward Current @ Test:350mA; Forward Current If Max:700mA; Forward Voltage @ Test:2.25V; Viewing Angle:100;RoHS Compliant: Yes |
| XR7090AM-L1-0001 | 制造商:Cree 功能描述:LED Uni-Color Amber 2-Pin SMD |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。