FIGURE 7. XR19L402 TRANSMITTER AND R
參數(shù)資料
型號: XR19L402IL48-0B-EB
廠商: Exar Corporation
文件頁數(shù): 5/49頁
文件大小: 0K
描述: EVAL BOARD FOR XR19L402-B 48QFN
標準包裝: 1
系列: *
FIGURE 7. XR19L402 TRANSMITTER AND RECEIVER
Charge Pump
AC
P
C1+
C1-
RXA+
RXA-
TXA+
TXA-
UART
RS-485 Transceiver
RXB
TXB
RXB+
RXB-
TXB+
TXB-
RXBSEL
RXB
TXB
RXA
TXA
XR19L402
13
REV. 1.0.3
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
2.10
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X internal
clock. A bit time is 16 (8) clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the
number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and
TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
2.10.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.10.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
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