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參數(shù)資料
| 型號(hào)： | XR19L402IL48-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 30/49頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR19L402-B 48QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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XR19L402
36
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. 1.0.3
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.17
RX/TX FIFO Level Count Register (FC) - Read-Only
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See Table 12.
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register. Reading this register is not recommended when transmitting
or receiving data.
4.18
Feature Control Register (FCTR) - Read/Write
FCTR[1:0]: Reserved
For normal operation, these bits should remain a logic 0.
FCTR[2]: IrDa RX Inversion
Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).
FCTR[3]: Auto Half-Duplex Direction Control
This bit overrides the HALF/FULL# pin to enable half-duplex mode or full-duplex mode.
Logic 0 = Full-duplex mode. In this mode, the transmit interrupt is generated when the transmit holding
register becomes empty and the transmit shift register is shifting data out.
Logic 1 = Auto half-duplex mode. In this mode, the direction of the RS-485 transceiver is internally controlled
by the RTS# signal. Also, the transmit interrupt generation is delayed until the transmitter shift register
becomes empty.
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
TABLE 14: TRIGGER TABLE SELECT
BIT-5
BIT-4
TABLE
0
Table-A (TX/RX)
0
1
Table-B (TX/RX)
1
0
Table-C (TX/RX)
1
Table-D (TX/RX)
Table 10 for more details.
FCTR[6]: Scratchpad Swap
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Level Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
FCTR
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