REV. 1.0.3 TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU in" />
參數(shù)資料
型號： XR19L402IL48-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 47/49頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR19L402-B 48QFN
標準包裝： 1
系列： *
XR19L402
7
REV. 1.0.3
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L402 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus
interconnection for Intel and Motorola mode is shown in Figure 4.
FIGURE 4. XR19L402 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
VCC3 .3
VCC3.3
RXB
TXB +
GND
UART
Channel A
UART
Channel B
Intel Data Bus Interconnections
TXB
RS-485 Interface
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A0
A1
A2
UART_CSA #
UART_CSB #
IOR #
IOW #
CSA #
CSB #
IOR#
IOW #
UART_INTB
UART_INTA
INTB
INTA
ACP
R_EN
RESET
R_EN
PW RSAVE
ACP
RXBSEL
UART_RESET
PW RSAVE
External IR or RS -232
Transceiver
VCC5 .0
VCC5.0
RXA +
RXA-
TXA +
TXA -
RXB-
TXB -
RXB +
RS-485 Interface
HALF /FULLB #
HALF /FULLA #
GND
UART
Channel A
UART
Channel B
Motorola Data Bus Interconnections
UART_IRQ#
INTA
VCC
INTB
(no connect )
R_EN
ACP
RXBSEL
HALF/FULLA #
HALF /FULLA #
PW RSAVE
RESET
UART_RESET
External IR or RS -232
transceiver
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
VCC
R/W #
IOW #
UART_CS#
CSA#
A3
CSB#
HALF/FULLB #
HALF /FULLB #
VCC3. 3
VCC3.3
VCC5. 0
VCC5.0
RS-485 Interface
RXA -
TXA-
RXA+
TXA+
RS-485 Interface
RXB -
TXB -
RXB+
TXB+
TXB
RXB
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