REV. 1.0.3 TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER AC ELECTRICAL CHARACTERISTICS U
參數(shù)資料
型號(hào)： XR19L402IL48-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 36/49頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR19L402-B 48QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR19L402
41
REV. 1.0.3
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC=3.3 OR 5V ± 10%, 70 PF LOAD WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
3.3
MIN
MAX
LIMITS
5.0
MIN
MAX
UNIT
-
Crystal Frequency
24
MHz
OSC
External Clock Frequency
64
MHz
CLK
External Clock Low/High Time
7
ns
TAS
Address Setup Time (16 Mode)
0
ns
TAH
Address Hold Time (16 Mode)
0
ns
TCS
Chip Select Width (16 Mode)
65
ns
TRD
IOR# Strobe Width (16 Mode)
65
ns
TDY
Read Cycle Delay (16 Mode)
65
ns
TRDV
Data Access Time (16 Mode)
60
ns
TDD
Data Disable Time (16 Mode)
0
15
0
15
ns
TWR
IOW# Strobe Width (16 Mode)
65
ns
TDY
Write Cycle Delay (16 Mode)
65
ns
TDS
Data Setup Time (16 Mode)
10
ns
TDH
Data Hold Time (16 Mode)
5
ns
TADS
Address Setup (68 Mode)
0
ns
TADH
Address Hold (68 Mode)
0
ns
TRWS
R/W# Setup to CS# (68 Mode)
0
ns
TRDA
Read Data Access (68 mode)
60
ns
TRDH
Read Data Disable Time (68 mode)
0
15
0
15
ns
TWDS
Write Data Setup (68 mode)
10
ns
TWDH
Write Data Hold (68 Mode)
5
ns
TRWH
CS# De-asserted to R/W# De-asserted (68 Mode)
5
ns
TCSL
CS# Width (68 Mode)
65
ns
TCSD
CS# Cycle Delay (68 Mode)
65
ns
TWDO
Delay From IOW# To Output
50
ns
TMOD
Delay To Set Interrupt From MODEM Input
50
ns
TRSI
Delay To Reset Interrupt From IOR#
50
ns
TSSI
Delay From Stop To Set Interrupt
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
50
ns
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