Table 12 provides the I
參數(shù)資料
型號(hào)： XPC8240LVV200E
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 13/52頁(yè)
文件大小： 0K
描述： IC MPU INTEGRATED 200MHZ 352TBGA
標(biāo)準(zhǔn)包裝： 24
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 200MHz
電壓： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 352-LBGA
供應(yīng)商設(shè)備封裝： 352-TBGA（35x35）
包裝： 托盤(pán)
20
MPC8240 Integrated Processor Hardware Specifications
Electrical and Thermal Characteristics
Table 12 provides the I2C frequency divider register (I2CFDR) information for the MPC8240.
4
Data hold time
0
—
ns
2
5
SCL/SDA fall time (from 2.4 to 0.5 V)
—
1
ms
6
Clock high period (time needed to either receive
a data bit or generate a START or STOP)
5.0
—
CLKs
1, 2, 5
7
Data setup time
3.0
—
ns
3
8
Start condition setup time (for repeated start
condition only)
4.0
—
CLKs
1, 2
9
Stop condition setup time
4.0
—
CLKs
1, 2
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency
divider register I2CFDR. Therefore, the noted timings in this table are all relative to qualified signals. The qualified
SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL and SDA signals
are delayed by the SDRAM_CLK clock times DFFSR times two plus one SDRAM_CLK clock. The resulting delay
value is added to the value in the table (where this note is referenced). See Figure 13.
3. Timing is relative to the sampling clock (not SCL).
4. FDR[x] refers to the frequency divider register I2CFDR bit n.
5. Input clock low and high periods in combination with the FDR value in the frequency divider register (I2CFDR)
determine the maximum I2C input frequency. See Table 12.
Table 12. MPC8240 Maximum I2C Input Frequency
FDR Hex 2
Divider 3 (Dec)
Maximum I2C Input Frequency 1
SDRAM_CLK
@ 33 MHz
SDRAM_CLK
@ 50 MHz
SDRAM_CLK
@ 100 MHz
20, 21
160, 192
1.13 MHz
1.72 MHz
3.44 MHz
22, 23, 24, 25
224, 256, 320, 384
733
1.11 MHz
2.22 MHz
0, 1
288, 320
540
819
1.63 MHz
2, 3, 26, 27, 28, 29
384, 448, 480, 512, 640, 768
428
649
1.29 MHz
4, 5
576, 640
302
458
917
6, 7, 2A, 2B, 2C, 2D
768, 896, 960, 1024, 1280, 1536
234
354
709
8, 9
1152, 1280
160
243
487
A, B, 2E, 2F, 30, 31
1536, 1792, 1920, 2048, 2560, 3072
122
185
371
C, D
2304, 2560
83
125
251
E, F, 32, 33, 34, 35
3072, 3584, 3840, 4096, 5120, 6144
62
95
190
10, 11
4608, 5120
42
64
128
12, 13, 36, 37, 38, 39
6144, 7168, 7680, 8192, 10240, 12288
31
48
96
Table 11. I2C Input AC Timing Specifications
At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V
Num
Characteristic
Min
Max
Unit
Notes
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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