參數(shù)資料
型號： XPC755BRX400LE
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 39/52頁
文件大小： 1274K
代理商： XPC755BRX400LE
MOTOROLA
MPC755 RISC Microprocessor Hardware Specifications
39
System Design Information
Figure 24. JTAG Interface Connection
There is no standardized way to number the COP header shown in Figure 24; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
HRESET
HRESET
From Target
Board Sources
HRESET
13
SRESET
SRESET
SRESET
NC
NC
11
VDD_SENSE
6
5
1
15
2 k
10 k
10 k
10 k
OV
DD
OV
DD
OV
DD
OV
DD
CHKSTP_IN
CHKSTP_IN
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
C
14
2
Key
QACK
OV
DD
OV
DD
10 k
OV
DD
TRST
10 k
OV
DD
10 k
10 k
QACK
QACK
CHKSTP_OUT
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
COP Connector
Physical Pin Out
10 k
4
OV
DD
2 k
3
0
5
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC755. Connect
pin 5 of the COP header to OV
DD
with a 10-k
pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-
isolation reisistor.
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