參數(shù)資料
型號(hào)： XPC750EC
英文描述： XPC750P/D XPC750P RISC Microprocessor Hardware Specifications
中文描述： XPC750P /數(shù)XPC750P RISC微處理器硬件規(guī)格
文件頁(yè)數(shù)： 1/52頁(yè)
文件大?。?/td> 1274K
代理商： XPC750EC
This document is primarily concerned with the MPC755; however, unless otherwise noted, all
information here also applies to the MPC745. The MPC755 and MPC745 are reduced
instruction set computing (RISC) microprocessors that implement the PowerPC instruction
set architecture. This document describes pertinent physical characteristics of the MPC755.
For functional characteristics of the processor, refer to the
MPC750 RISC Microprocessor
Family User’s Manual
.
This document contains the following topics:
Topic
Section 1.1, “Overview”
Section 1.2, “Features”
Section 1.3, “General Parameters”
Section 1.4, “Electrical and Thermal Characteristics”
Section 1.5, “Pin Assignments”
Section 1.6, “Pinout Listings”
Section 1.7, “Package Description”
Section 1.8, “System Design Information”
Section 1.9, “Document Revision History”
Section 1.10, “Ordering Information”
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/semiconductors.
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1.1
Overview
The MPC755 is targeted for low-cost, low-power systems and supports the following power
management features—doze, nap, sleep, and dynamic power management. The MPC755
consists of a processor core and an internal L2 tag combined with a dedicated L2 cache
interface and a 60x bus. The MPC745 is identical to the MPC755 except it does not support
the L2 cache interface.
Figure 1 shows a block diagram of the MPC755.
Advance Information
MPC755EC/D
Rev. 5, 6/2002
MPC755 RISC
Mcroprocessor
Hardware Specifications
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