參數(shù)資料
型號(hào): XCCACE128-I
廠商: Xilinx Inc
文件頁數(shù): 6/69頁
文件大小: 0K
描述: IC 128MBIT ACE FLASH CARD
標(biāo)準(zhǔn)包裝: 1
存儲(chǔ)容量: 128Mb
存儲(chǔ)器類型: FLASH
System ACE CompactFlash Solution
14
DS080 (v3.0) April 7, 2014
Product Specification
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Single Register Write Cycle
The single register write cycle is shown in Figure 10. A sin-
gle register write is accomplished by asserting a valid
address (MPA), asserting the chip enable (MPCE = LOW)
and de-asserting the output enable (MPOE = HIGH) during
the first clock cycle (Cycle 0). These signals should hold
these values at least until the rising edge of the third clock
cycle (Cycle 2).
The write enable signal should be asserted (MPWE = LOW)
during the second clock cycle (Cycle 1). Data (MPD) to be
written to the specified address should be asserted during
the same clock cycle that the write enable is asserted
(Cycle 1). The register write cycle is then completed by
de-asserting the write enable during the third clock cycle
(Cycle 2).
Figure 10: Single WORD Write to an ACE Register
60ns
80ns
100ns
120ns
140ns
160 s
CYCLE
CLK
MPA
MPD
MPCE
MPWE
MPOE
Cycle 0
Cycle 1
Cycle 2
Cycle 3
ADDRESS
DATA
tSA
tSCE
tH
tSWE
tH
tSD
tH
tSOE
DS080_15_013101
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