參數(shù)資料
型號: XC6SLX75T-2FG676I
廠商: Xilinx Inc
文件頁數(shù): 76/89頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 676FGGBGA
標準包裝: 40
系列: Spartan® 6 LXT
LAB/CLB數(shù): 5831
邏輯元件/單元數(shù): 74637
RAM 位總計: 3170304
輸入/輸出數(shù): 348
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應商設備封裝: 676-FBGA(27x27)
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
78
Table 76: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-3
-3N
-2
-1L
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSDCMPLL/
TPHDCMPLL
No Delay Global Clock and IFF(2)
with DCM in System-Synchronous
Mode and PLL in DCM2PLL Mode.
XC6SLX4
1.16/0.49
N/A
1.39/0.49
2.36/0.59
ns
XC6SLX9
1.16/0.44
1.37/0.44
1.39/0.44
2.36/0.59
ns
XC6SLX16
1.44/–0.08
1.49/–0.04
1.62/–0.04
2.06/0.55
ns
XC6SLX25
1.52/0.42
1.65/0.42
1.83/0.42
2.52/0.43
ns
XC6SLX25T
1.52/0.42
1.65/0.42
1.83/0.42
N/A
ns
XC6SLX45
1.54/0.39
1.59/0.39
1.75/0.39
2.48/0.76
ns
XC6SLX45T
1.54/0.39
1.59/0.39
1.75/0.39
N/A
ns
XC6SLX75
1.72/0.41
1.80/0.41
1.99/0.41
2.60/0.75
ns
XC6SLX75T
1.72/0.41
1.80/0.41
1.99/0.41
N/A
ns
XC6SLX100
1.34/0.51
1.46/0.51
1.64/0.51
2.12/0.90
ns
XC6SLX100T
1.34/0.51
1.46/0.51
1.64/0.51
N/A
ns
XC6SLX150
1.30/0.60
1.40/0.60
1.55/0.60
2.57/0.97
ns
XC6SLX150T
1.30/0.60
1.40/0.60
1.55/0.60
N/A
ns
XA6SLX4
1.58/0.37
N/A
1.58/0.37
N/A
ns
XA6SLX9
1.58/0.37
N/A
1.58/0.37
N/A
ns
XA6SLX16
2.67/0.35
N/A
2.67/0.17
N/A
ns
XA6SLX25
1.74/0.27
N/A
1.95/0.27
N/A
ns
XA6SLX25T
1.74/0.27
N/A
2.03/0.27
N/A
ns
XA6SLX45
1.58/0.29
N/A
1.87/0.29
N/A
ns
XA6SLX45T
1.58/0.29
N/A
1.87/0.29
N/A
ns
XA6SLX75
1.74/0.24
N/A
2.11/0.24
N/A
ns
XA6SLX75T
1.74/0.24
N/A
2.11/0.24
N/A
ns
XA6SLX100
N/A
2.64/0.82
N/A
ns
XQ6SLX75
N/A
2.11/0.24
2.60/0.75
ns
XQ6SLX75T
1.74/0.24
N/A
2.11/0.24
N/A
ns
XQ6SLX150
N/A
1.67/0.70
2.57/0.97
ns
XQ6SLX150T
1.50/0.70
N/A
1.67/0.70
N/A
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0
driving BUFG.
2.
IFF = Input Flip-Flop or Latch
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
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