參數(shù)資料
型號(hào)： XC6SLX75T-2FG676I
廠商： Xilinx Inc
文件頁數(shù)： 45/89頁
文件大小： 0K
描述： IC FPGA SPARTAN 6 676FGGBGA
標(biāo)準(zhǔn)包裝： 40
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 5831
邏輯元件/單元數(shù)： 74637
RAM 位總計(jì)： 3170304
輸入/輸出數(shù)： 348
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
5
Table 4: DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
Typ
Max
Units
VDRINT
Data retention VCCINT voltage (below which configuration data might be lost)
0.8
–
V
VDRAUX
Data retention VCCAUX voltage (below which configuration data might be lost)
2.0
–
V
IREF
VREF leakage current per pin for commercial (C) and industrial (I) devices
–10
–
10
A
VREF leakage current per pin for expanded (Q) devices
–15
–
15
A
IL
Input or output leakage current per pin (sample-tested) for commercial (C) and industrial
(I) devices
–10
–
10
A
Input or output leakage current per pin (sample-tested) for expanded (Q) devices
–15
–
15
A
IHS
Leakage current on pins during hot
socketing with FPGA unpowered
All pins except PROGRAM_B, DONE, and
JTAG pins when HSWAPEN = 1
–20
–
20
A
PROGRAM_B, DONE, and JTAG pins, or other
pins when HSWAPEN = 0
IHS + IRPU
A
CIN(1)
Die input capacitance at the pad
–
10
pF
IRPU
Pad pull-up (when selected) @ VIN =0V, VCCO =3.3V or VCCAUX = 3.3V
200
–
500
A
Pad pull-up (when selected) @ VIN =0V, VCCO =2.5V or VCCAUX = 2.5V
120
–
350
A
Pad pull-up (when selected) @ VIN =0V, VCCO = 1.8V
60
–
200
A
Pad pull-up (when selected) @ VIN =0V, VCCO = 1.5V
40
–
150
A
Pad pull-up (when selected) @ VIN =0V, VCCO = 1.2V
12
–
100
A
IRPD
Pad pull-down (when selected) @ VIN =VCCO, VCCAUX = 3.3V
200
–
550
A
Pad pull-down (when selected) @ VIN =VCCO, VCCAUX = 2.5V
140
–
400
A
IBATT(2)
Battery supply current
–
150
nA
RDT(3)
Resistance of optional input differential termination circuit, VCCAUX =3.3V
–
100
–
RIN_TERM(5)
Thevenin equivalent resistance of programmable input termination to VCCO
(UNTUNED_SPLIT_25) for commercial (C) and industrial (I) devices
23
25
55
Thevenin equivalent resistance of programmable input termination to VCCO
(UNTUNED_SPLIT_25) for expanded (Q) devices
20
25
55
Thevenin equivalent resistance of programmable input termination to VCCO
(UNTUNED_SPLIT_50) for commercial (C) and industrial (I) devices
39
50
72
Thevenin equivalent resistance of programmable input termination to VCCO
(UNTUNED_SPLIT_50) for expanded (Q) devices
32
50
74
Thevenin equivalent resistance of programmable input termination to VCCO
(UNTUNED_SPLIT_75) for commercial (C) and industrial (I) devices
56
75
109
Thevenin equivalent resistance of programmable input termination to VCCO
(UNTUNED_SPLIT_75) for expanded (Q) devices
47
75
115
ROUT_TERM
Thevenin equivalent resistance of programmable output termination (UNTUNED_25)
11
25
52
Thevenin equivalent resistance of programmable output termination (UNTUNED_50)
21
50
96
Thevenin equivalent resistance of programmable output termination (UNTUNED_75)
29
75
145
Notes:
1.
The CIN measurement represents the die capacitance at the pad, not including the package.
2.
Maximum value specified for worst case process at 25°C. LX75, LX75T, LX100, LX100T, LX150, and LX150T only.
3.
Refer to IBIS models for RDT variation and for values at VCCAUX = 2.5V. IBIS values for RDT are valid for all temperature ranges.
4.
VCCO2 is not required for data retention. The minimum VCCO2 for power-on reset and configuration is 1.65V.
5.
Termination resistance to a VCCO/2 level.
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XC6SLX75T-2FGG676I IC FPGA SPARTAN 6 74K 676FGGBGA
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