參數(shù)資料
型號: XC6SLX75T-2FG676I
廠商: Xilinx Inc
文件頁數(shù): 55/89頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 676FGGBGA
標(biāo)準(zhǔn)包裝: 40
系列: Spartan® 6 LXT
LAB/CLB數(shù): 5831
邏輯元件/單元數(shù): 74637
RAM 位總計: 3170304
輸入/輸出數(shù): 348
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
59
Table 54: Switching Characteristics for the Delay-Locked Loop (DLL)(1)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Min
Max
Min
Max
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and
CLK180 outputs.
5
280
5
280
5
250
5
175
MHz
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and
CLK270 outputs.
5
200
5
200
5
200
5
175
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and
CLK2X180 outputs.
10
375
10
375
10
334
10
250
MHz
CLKOUT_FREQ_DV
Frequency for the CLKDV output.
0.3125
186
0.3125
186
0.3125
166
0.3125
88.6
MHz
Output Clock Jitter(2)(3)(4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output.
±100
±100
±100
±100
ps
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output.
±150
±150
±150
±150
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output.
±150
±150
±150
±150
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output.
±150
±150
±150
±150
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and
CLK2X180 outputs.
Maximum = ±[0.5% of CLKIN period + 100]
ps
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV output
when performing integer division.
±150
±150
±150
±150
ps
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output
when performing non-integer
division.
Maximum = ±[0.5% of CLKIN period + 100]
ps
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0,
CLK90, CLK180, CLK270, CLK2X,
CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock
tree duty-cycle distortion.
Typical = ±[1% of CLKIN period + 350]
ps
Phase Alignment(4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN
and CLKFB inputs
(CLK_FEEDBACK = 1X).
±150
±150
±150
±250
ps
Phase offset between the CLKIN
and CLKFB inputs
(CLK_FEEDBACK = 2X).(6)
±250
±250
±250
±350
CLKOUT_PHASE_DLL
Phase offset between DLL outputs
for CLK0 to CLK2X (not CLK2X180).
Maximum = ±[1% of CLKIN period + 100]
ps
Phase offset between DLL outputs
for all others.
Maximum = ±[1% of CLKIN period + 150]
Maximum =
±[1% of
CLKIN
period + 200]
ps
相關(guān)PDF資料
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XC6SLX75T-2FGG676I IC FPGA SPARTAN 6 74K 676FGGBGA
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