參數(shù)資料
型號: XC6SLX45T-2FG484I
廠商: Xilinx Inc
文件頁數(shù): 69/89頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 484FGGBGA
標準包裝: 60
系列: Spartan® 6 LXT
LAB/CLB數(shù): 3411
邏輯元件/單元數(shù): 43661
RAM 位總計: 2138112
輸入/輸出數(shù): 296
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應商設備封裝: 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
71
Table 69: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-3
-3N
-2
-1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode
and PLL in DCM2PLL Mode.
TICKOFDCM0_PLL
Global Clock and OUTFF with DCM and PLL
XC6SLX4
5.58
N/A
7.42
8.54
ns
XC6SLX9
5.586.197.428.54
ns
XC6SLX16
5.50
6.06
7.05
8.24
ns
XC6SLX25
5.57
6.04
7.02
8.33
ns
XC6SLX25T
5.57
6.04
7.02
N/A
ns
XC6SLX45
5.53
5.97
6.96
8.32
ns
XC6SLX45T
5.53
5.97
6.96
N/A
ns
XC6SLX75
5.55
6.00
6.99
8.54
ns
XC6SLX75T
5.55
6.00
6.99
N/A
ns
XC6SLX100
5.586.037.029.11
ns
XC6SLX100T
5.62
6.03
7.02
N/A
ns
XC6SLX150
5.325.706.418.26
ns
XC6SLX150T
5.32
5.70
6.41
N/A
ns
XA6SLX4
5.87
N/A
7.28
N/A
ns
XA6SLX9
5.87
N/A
7.28
N/A
ns
XA6SLX16
6.02
N/A
6.87
N/A
ns
XA6SLX25
5.88
N/A
6.90
N/A
ns
XA6SLX25T
5.88
N/A
7.00
N/A
ns
XA6SLX45
5.82
N/A
6.81
N/A
ns
XA6SLX45T
5.82
N/A
6.81
N/A
ns
XA6SLX75
5.81
N/A
6.80
N/A
ns
XA6SLX75T
5.81
N/A
6.80
N/A
ns
XA6SLX100
N/A
6.88
N/A
ns
XQ6SLX75
N/A
6.80
8.54
ns
XQ6SLX75T
5.81
N/A
6.80
N/A
ns
XQ6SLX150
N/A
6.41
8.26
ns
XQ6SLX150T
5.90
N/A
6.41
N/A
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
2.
DCM and PLL output jitter are already included in the timing calculation.
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