參數(shù)資料
型號(hào)： XC6SLX45T-2FG484I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 14/89頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 6 484FGGBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 3411
邏輯元件/單元數(shù)： 43661
RAM 位總計(jì)： 2138112
輸入/輸出數(shù)： 296
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
21
IOB Pad Input/Output/3-State Switching Characteristics
Table 28 (for commercial (XC) Spartan-6 devices) and Table 29 (for Automotive XA Spartan-6 and Defense-grade
Spartan-6Q devices) summarizes the values of standard-specific data input delays, output delays terminating at pads
(based on standard), and 3-state delays.
TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer.
See the TRACE report for further information on delays when using an I/O standard with UNTUNED termination on inputs
or outputs.
XQ6SLX75
N/A
ISE 13.2 v1.19
ISE 13.2 v1.07
XQ6SLX75T
ISE 13.2 v1.19
N/A
ISE 13.2 v1.19
N/A
XQ6SLX150
N/A
ISE 13.2 v1.19
ISE 13.2 v1.07
XQ6SLX150T
ISE 13.2 v1.19
N/A
ISE 13.2 v1.19
N/A
Notes:
1.
ISE 13.3 software with v1.20 for -3, -3N, and -2; and v1.08 for -1L speed specification reflects the changes outlined in
XCN11028: Spartan-6 FPGA Speed File Changes.
2.
As marked with an N/A, LXT devices and all XA devices are not available with a -1L speed grade; LX4 devices and all XA and XQ devices
are not available with a -3N speed grade.
3.
Improved -3 specifications reflected in this data sheet require ISE 12.4 software with v1.15 speed specification.
4.
Improved -2 specifications reflected in this data sheet require ISE 12.4 software and the 12.4 Speed Files Patch which contains the v1.17
speed specification available on the Xilinx Download Center.
5.
ISE 12.3 software with v1.12 speed specification is available using ISE 12.3 software and the 12.3 Speed Files Patch available on the
6.
ISE 12.2 software with v1.11 speed specification is available using ISE 12.2 software and the 12.2 Speed Files Patch available on the
7.
ISE 13.1 software with v1.18 speed specification is available using ISE 13.1 software and the 13.1 Update available on the
Xilinx Download Center. See XCN11012: Speed File Change for -3N Devices.
Table 28: IOB Switching Characteristics for the Commercial (XC) Spartan-6 Devices
I/O Standard
TIOPI
TIOOP
TIOTP
Units
Speed Grade
-3
-3N
-2
-3
-3N
-2
-1L(1)
-3
-3N
-2
-1L(1)
LVDS_33
1.17
1.29
1.42
1.68
1.55
1.69
1.89
2.42
3000
ns
LVDS_25
1.01
1.13
1.26
1.57
1.65
1.79
1.99
2.47
3000
ns
BLVDS_25
1.02
1.14
1.27
1.57
1.72
1.86
2.06
2.68
1.72
1.86
2.06
2.68
ns
MINI_LVDS_33
1.17
1.29
1.42
1.68
1.57
1.71
1.91
3000
ns
MINI_LVDS_25
1.01
1.13
1.26
1.57
1.65
1.79
1.99
2.47
3000
ns
LVPECL_33
1.18
1.30
1.43
1.68
N/A
ns
LVPECL_25
1.02
1.14
1.27
1.57
N/A
ns
RSDS_33 (point to point)
1.17
1.29
1.42
1.68
1.57
1.71
1.91
2.42
3000
ns
RSDS_25 (point to point)
1.01
1.13
1.26
1.56
1.65
1.79
1.99
2.47
3000
ns
TMDS_33
1.21
1.33
1.46
1.71
1.54
1.68
1.88
2.50
3000
ns
Table 27: Spartan-6 Device Production Software and Speed Specification Release(1) (Cont’d)
Device
Speed Grade Designations(2)
-3(3)
-3N
-2(4)
-1L
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XC6SLX45T-2FGG484C 功能描述:IC FPGA SPARTAN 6 43K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan® 6 LXT 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC6SLX45T-2FGG484CES9982 制造商:Xilinx 功能描述:
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