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參數(shù)資料
| 型號： | XC6SLX45T-2FG484I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 49/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN 6 484FGGBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan® 6 LXT |
| LAB/CLB數(shù)： | 3411 |
| 邏輯元件/單元數(shù)： | 43661 |
| RAM 位總計： | 2138112 |
| 輸入/輸出數(shù)： | 296 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-BBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA |
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
53
Table 45: Device DNA Interface Port Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
TDNASSU
Setup time on SHIFT before the rising edge of CLK
7
ns, Min
TDNASH
Hold time on SHIFT after the rising edge of CLK
1
ns, Min
TDNADSU
Setup time on DIN before the rising edge of CLK
7
ns, Min
TDNADH
Hold time on DIN after the rising edge of CLK
1
ns, Min
TDNARSU
Setup time on READ before the rising edge of CLK
7ns, Min
1,000
ns, Max
TDNARH
Hold time on READ after the rising edge of CLK
1
ns, Min
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
0.5
ns, Min
6ns, Max
TDNACLKF(2)
CLK frequency
2
MHz, Max
TDNACLKL
CLK Low time
50
ns, Min
TDNACLKH
CLK High time
50
ns, Min
Notes:
1.
The minimum READ pulse width is 8 ns, the maximum READ pulse width is 1 s.
2.
Also applies to TCK when reading DNA through the boundary-scan port.
Table 46: Suspend Mode Switching Characteristics
Symbol
Description
Min
Max
Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE
Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
2.5
14
ns
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled
31
430
ns
TSUSPEND_GWE
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior (without glitch filter)
–15
ns
TSUSPEND_GTS
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements (without glitch filter)
–15
ns
TSUSPEND_DISABLE
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled (without glitch filter)
–
1500
ns
Exiting Suspend Mode
TSUSPENDLOW_AWAKE
Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not
include DCM or PLL lock time.
775
s
TSUSPEND_ENABLE
Falling edge of the SUSPEND pin to FPGA input pins and interconnect re-
enabled
741
s
TAWAKE_GWE1
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
–80
ns
TAWAKE_GWE512
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
–20.5
s
TAWAKE_GTS1
Rising edge of the AWAKE pin until outputs return to the behavior described in
the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
–80
ns
TAWAKE_GTS512
Rising edge of the AWAKE pin until outputs return to the behavior described in
the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512.
–20.5
s
TSCP_AWAKE
Rising edge of SCP pins to rising edge of AWAKE pin
7
75
s
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC6SLX45T-2FGG484C | 功能描述:IC FPGA SPARTAN 6 43K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| XC6SLX45T-2FGG484CES9982 | 制造商:Xilinx 功能描述: |
| XC6SLX45T-2FGG484I | 功能描述:IC FPGA SPARTAN 6 43K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC6SLX45T-2FGG676C | 制造商:Xilinx 功能描述: |
| XC6SLX45T-2FGG676I | 制造商:Xilinx 功能描述: |
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